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pi7c9x110 pci express-to-pci reversible bridge revision 3.0 3545 north 1 st street, san jose, ca 95134 phone: 1-877-pericom (1-877-737-4266) fax: 1-408-435-1100 internet: http://www.pericom.com
pi7c9x110 pcie-to-pci reversible bridge page 2 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 life support policy pericom semiconductor corporation? s products are not authorized for use as criti cal components in life support devices or syste ms unless a specific written agreement pertaining to such intended use is ex ecuted between the manufacturer and an officer of psc. 1) life support devices or system are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and w hose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) a critical component is any component of a life support device or system whose failure to perf orm can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or e ffectiveness. pericom semiconductor corporation reserves the ri ght to make changes to its products or specifications at any time, without notice, in or der to improve design or performance and to supply the best po ssible product. pericom semiconductor does not assume any responsibility for use of any circ uitry described other than the circuitry embodied in a peri com semiconductor product. the company makes no representations that circuitry descri bed herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under an y patent, patent rights or other rights, of pericom semiconductor corporation. all other trademarks are of their respective companies.
pi7c9x110 pcie-to-pci reversible bridge page 3 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 revision history date revision # description 09/08/2006 2.0 first release of 9x110 datasheet without revision suffix 11/21/2006 2.1 removed references to pi7c9x110a 03/06/2007 2.2 revised esd ratings in ?dc specificati ons? section 16.2 05/02/2007 2.3 revised table 8-1 in section 8 address bit[5] corrected to equal 0 address bit[4] corrected to equal gpio[3] 11/02/2007 2.4 revised logos a nd font types and added industrial temp compliancy 01/03/2008 2.5 revised industrial temp compliancy 05/16/2008 2.6 revised minimum pc i frequency support to 10mhz added leaded part number ? PI7C9X110BNB 09/25/2008 2.6 added additional pin description to gpio [3:0] 08/21/2009 2.7 revised ordering info section for leaded part 09/14/2009 2.8 revised revision id register definition 10/10/2009 2.9 updated the pin descri ption of pci express signals 04/28/2010 3.0 pcix feature is removed from datasheets preface the datasheet of pi7c9x110 will be enhanced periodically when updated information is available. the technical information in this datasheet is subject to change without notice. this document describes the functionalities of pi7c9x110 (pci express bridge) and provides technical information for designers to design their hardware using pi7c9x110.
pi7c9x110 pcie-to-pci reversible bridge page 4 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 table of contents 1 introduction ................................................................................................................... ..... 14 1.1 pci expre ss features ....................................................................................................... ........................ 14 1.2 pci features....................................................................................................................... .......................... 15 1.3 general features ........................................................................................................... .......................... 15 2 pin definitions ................................................................................................................ ...... 16 2.1 signal types ............................................................................................................... .................................. 16 2.2 pci express signals........................................................................................................ ........................... 16 2.3 pci signals................................................................................................................ ..................................... 16 2.4 mode select and strapping signals .......................................................................................... ..... 18 2.5 jtag boundary scan signals ................................................................................................. ............. 18 2.6 miscellaneous signals...................................................................................................... .................... 18 2.7 power and ground pins...................................................................................................... .................... 19 2.8 pin assignments ............................................................................................................ ............................. 19 3 mode selection and pin strapping.......................................................................... 21 3.1 functio nal mode selection ............................................................................................................. .. 21 3.3 pin strapping.............................................................................................................. .................................. 21 4 forward and reverse bridging ................................................................................ 21 5 transparent and non-tr ansparent bridging.................................................. 24 5.1 transparent mode ........................................................................................................... ........................ 24 5.2 non-transparent mode....................................................................................................... ................... 24 6 pci express functional overview........................................................................... 26 6.1 tlp st ructure .............................................................................................................. ............................... 26 6.2 virtual isochr onous oper ation.............................................................................................. ......... 26 7 configuration registers.............................................................................................. 26 7.1 configuration register map ................................................................................................. ............. 27 7.2 pci express extended ca pability register map ........................................................................ 30 7.3 control and status register map............................................................................................ ....... 31 7.4 pci configuration registers for transparent bridge mode ............................................ 32 7.4.1 vendor id ? of fset 00h ......................................................................................................... ....... 33 7.4.2 device id ? offset 00h......................................................................................................... ......... 33 7.4.3 command register ? offset 04h .............................................................................................. 33 7.4.4 primary status register ? offset 04h................................................................................... 34 7.4.5 revision id regist er ? offset 08h ........................................................................................... 35 7.4.6 class code regist er ? offset 08h ........................................................................................... 35 7.4.7 cache line size regi ster ? offset 0ch.................................................................................. 35 7.4.8 primary latency timer register ? offset 0ch .................................................................. 36 7.4.9 primary header type register ? offset 0ch ...................................................................... 36 7.4.10 reserved registers ? of fset 10h to 17h................................................................................ 36 7.4.11 primary bus number register ? offset 18h ........................................................................ 36 7.4.12 secondary bus number reg ister ? offset 18h .................................................................. 36 7.4.13 subordinate bus number register ? offset 18h .............................................................. 36 7.4.14 secondary latency time re gister ? offset 18h................................................................ 36 7.4.15 i/o base register ? offset 1ch................................................................................................. .36
pi7c9x110 pcie-to-pci reversible bridge page 5 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.16 i/o limit register ? offset 1ch................................................................................................ .37 7.4.17 secondary status regist er ? offset 1ch ............................................................................ 37 7.4.18 memory base regist er ? offset 20h ....................................................................................... 38 7.4.19 memory limit regist er ? offset 20h ...................................................................................... 38 7.4.20 prefetchable memory base re gister ? offs et 24h......................................................... 38 7.4.21 prefetchable memory limit re gister ? offs et 24h........................................................ 38 7.4.22 prefetchable base upper 32-bit register ? offset 28h................................................. 40 7.4.23 prefetchable limit upper 32-bit register ? offset 2ch............................................... 40 7.4.24 i/o base upper 16-bit register ? offset 30h......................................................................... 40 7.4.25 i/o limit upper 16-bit re gister ? offset 30h........................................................................ 40 7.4.26 capability pointer ? offset 34h .............................................................................................. 40 7.4.27 expansion rom base address reg ister ? offset 38h ....................................................... 40 7.4.28 interrupt line register ? offset 3ch................................................................................... 40 7.4.29 interrupt pin register ? offset 3ch ..................................................................................... 41 7.4.30 bridge control register ? offset 3ch ................................................................................ 41 7.4.31 pci data buffering control register ? offset 40h ....................................................... 42 7.4.32 chip control 0 regist er ? offset 40h................................................................................... 43 7.4.33 reserved register ? offset 44h............................................................................................... 45 7.4.34 arbiter enable register ? offset 48h................................................................................... 45 7.4.35 arbiter mode register ? offset 48h...................................................................................... 45 7.4.36 arbiter priority regist er ? offset 48h ................................................................................ 46 7.4.37 reserved registers ? offset 4ch ? 64h .................................................................................. 47 7.4.38 express transmitter/receiver register ? offset 68h.................................................... 47 7.4.39 upstream memory write fragment control register ? offset 68h ....................... 48 7.4.40 reserved register ? offset 6ch .............................................................................................. 48 7.4.41 eeprom autoload control/status register ? offset 70h........................................... 48 7.4.42 reserved register ? offset 74h............................................................................................... 50 7.4.43 gpio data and control register ? of fset 78h.................................................................. 50 7.4.44 reserved register ? offset 7ch .............................................................................................. 50 7.4.45 capability id regist er ? offset 80h ...................................................................................... 50 7.4.46 next capability pointer register ? offset 80h ................................................................ 50 7.4.47 secondary status register ? offset 80h............................................................................ 50 7.4.48 bridge status register ? offset 84h .................................................................................... 51 7.4.49 upstream split transaction register ? offset 88h ........................................................ 52 7.4.50 downstream split transaction register ? offset 8ch ................................................. 52 7.4.51 power management id reg ister ? offs et 90h.................................................................... 53 7.4.52 next capability pointer register ? offset 90h ................................................................ 53 7.4.53 power management capability register ? offset 90h .................................................. 53 7.4.54 power management control and status register ? offset 94h .............................. 54 7.4.55 pci-to-pci support extension register ? offset 94h ..................................................... 54 7.4.56 reserved registers ? of fset 98h ? 9ch .................................................................................. 54 7.4.57 capability id register ? offset a0h....................................................................................... 54 7.4.58 next pointer register ? offset a0h....................................................................................... 54 7.4.59 slot number register ? offset a0h ....................................................................................... 55 7.4.60 chassis number regist er ? offset a0h ................................................................................. 55 7.4.61 secondary clock and clkrun cont rol register ? offset a4h................................. 55 7.4.62 capability id register ? offset a8h....................................................................................... 56 7.4.63 next pointer register ? offset a8h....................................................................................... 56 7.4.64 reserved register ? offset a8h .............................................................................................. 56 7.4.65 subsystem vendor id register ? offset ach...................................................................... 57 7.4.66 subsystem id register ? offset ach ...................................................................................... 57 7.4.67 pci express capability id re gister ? offset b0h .............................................................. 57
pi7c9x110 pcie-to-pci reversible bridge page 6 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.68 next capability pointer re gister ? offset b0h ................................................................ 57 7.4.69 pci express capability regis ter ? offset b0h ................................................................... 57 7.4.70 device capability regi ster ? offset b4h............................................................................. 57 7.4.71 device control regist er ? offset b8h................................................................................. 58 7.4.72 device status register ? offset b8h..................................................................................... 59 7.4.73 link capability regist er ? offset bch ................................................................................. 59 7.4.74 link control register ? offset c0h...................................................................................... 60 7.4.75 link status register ? offset c0h.......................................................................................... 60 7.4.76 slot capability regist er ? offset c4h ................................................................................. 61 7.4.77 slot control register ? offset c8h ..................................................................................... 61 7.4.78 slot status register ? offset c8h ......................................................................................... 62 7.4.79 xpip configuration register 0 ? offset cch..................................................................... 62 7.4.80 xpip configuration register 1 ? offset d0h ..................................................................... 62 7.4.81 xpip configuration register 2 ? offset d4h ..................................................................... 62 7.4.82 hot swap switch debounce counter ? offset d4h......................................................... 64 7.4.83 capability id regist er ? offset d8h ...................................................................................... 64 7.4.84 next pointer register ? offset d8h ...................................................................................... 64 7.4.85 vpd register ? offset d8h ...................................................................................................... ... 64 7.4.86 vpd data register ? offset dch.............................................................................................. 64 7.4.87 reserved registers ? offset e0h ? ech ................................................................................. 65 7.4.88 message signaled interrupt s id regist er ? f0h............................................................... 65 7.4.89 next capabilities poin ter register ? f0h............................................................................ 65 7.4.90 message control register ? offset f0h ............................................................................. 65 7.4.91 message address register ? offset f4h .............................................................................. 65 7.4.92 message upper address regi ster ? offset f8h................................................................. 65 7.4.93 message data register ? offset fch..................................................................................... 66 7.4.94 advance error reporting capability id register ? offset 100h .............................. 66 7.4.95 advance error reporting capability ver sion register ? offset 100h .................. 66 7.4.96 next capability offset register ? offset 100h ................................................................ 66 7.4.97 uncorrectable error status register ? o ffset 104h ................................................... 66 7.4.98 uncorrectable error mask register ? offset 108h ...................................................... 66 7.4.99 uncorrectable error severity register ? offset 10ch............................................... 67 7.4.100 correctable error status re gister ? offs et 110h......................................................... 67 7.4.101 correctable error mask regi ster ? offset 114h ............................................................ 67 7.4.102 advanced error capabilities and control register ? offset 118h........................ 68 7.4.103 header log register 1 ? offset 11ch .................................................................................... 68 7.4.104 header log register 2 ? offset 120h..................................................................................... 68 7.4.105 header log register 3 ? offset 124h..................................................................................... 68 7.4.106 header log register 4 ? offset 128h..................................................................................... 68 7.4.107 secondary uncorrectable error status register ? offset 12ch ........................... 68 7.4.108 secondary uncorrectable error ma sk register ? offset 130h ............................... 69 7.4.109 secondary uncorrectable error severity register ? offset 134h ........................ 69 7.4.110 secondary error capability and control register ? offset 138h.......................... 70 7.4.111 secondary header log register ? offset 13ch ? 148h.................................................... 70 7.4.112 reserved register ? offset 14ch ............................................................................................ 70 7.4.113 vc capability id regis ter ? offset 150h ............................................................................... 70 7.4.114 vc capability version reg ister ? offset 150h ................................................................... 70 7.4.115 next capability offset register ? offset 150h ................................................................ 71 7.4.116 port vc capability regist er 1 ? offset 154h ...................................................................... 71 7.4.117 port vc capability regist er 2 ? offset 158h ...................................................................... 71 7.4.118 port vc control register ? offset 15ch............................................................................. 71 7.4.119 port vc status register ? offset 15ch................................................................................. 71
pi7c9x110 pcie-to-pci reversible bridge page 7 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.120 vc0 resource capability re gister ? offset 160h ............................................................. 71 7.4.121 vc0 resource control reg ister ? offset 164h ................................................................. 71 7.4.122 vc0 resource status register ? offset 168h ..................................................................... 72 7.4.123 reserved registers ? of fset 16ch ? 300h .............................................................................. 72 7.4.124 extra gpi/gpo data and control register ? offset 304h............................................. 72 7.4.125 reserved registers ? of fset 308h ? 30ch .............................................................................. 72 7.4.126 replay and acknowledge latency timers ? offset 310h ............................................. 72 7.4.127 reserved registers ? of fset 314h ? ffch ............................................................................. 72 7.5 pci configuration registers for non-transparent bridge mode..... 73 7.5.1 vendor id ? of fset 00h ......................................................................................................... ....... 73 7.5.2 device id ? offset 00h......................................................................................................... ......... 73 7.5.3 command register ? offset 04h .............................................................................................. 73 7.5.4 primary status register ? offset 04h................................................................................... 74 7.5.5 revision id regist er ? offset 08h ........................................................................................... 75 7.5.6 class code regist er ? offset 08h ........................................................................................... 75 7.5.7 cache line size regi ster ? offset 0ch.................................................................................. 76 7.5.8 primary latency timer register ? offset 0ch .................................................................. 76 7.5.9 primary header type register ? offset 0ch ...................................................................... 76 7.5.10 primary csr and memory 0 base address register ? offset 10h................................ 76 7.5.11 primary csr i/o base address register ? offset 14h ....................................................... 77 7.5.12 downstream i/o or memory 1 base address register ? offset 18h .......................... 77 7.5.13 donwstream memory 2 base address register ? offset 1ch ...................................... 78 7.5.14 downstream memory 3 base addres s register ? offset 20h....................................... 78 7.5.15 downstream memory 3 upper base address register ? offset 24h ......................... 79 7.5.16 reserved register ? offset 28h............................................................................................... 79 7.5.17 subsytem id and subsystem vendor id register ? offset 2ch.................................... 79 7.5.18 reserved register ? offset 30h............................................................................................... 79 7.5.19 capability pointer ? offset 34h .............................................................................................. 79 7.5.20 expansion rom base address reg ister ? offset 38h ....................................................... 79 7.5.21 primary interrupt line reg ister ? offset 3ch ................................................................. 79 7.5.22 primary interrupt pin reg ister ? offset 3ch.................................................................... 79 7.5.23 primary minimum grant register ? offset 3ch ................................................................ 80 7.5.24 primary maximum latency time register ? offset 3ch................................................. 81 7.5.25 pci data buffering control register ? offset 40h ....................................................... 81 7.5.26 chip control 0 regist er ? offset 40h................................................................................... 82 7.5.27 secondary command register ? offset 44h ...................................................................... 83 7.5.28 secondary status regist er ? offset 44h............................................................................. 84 7.5.29 arbiter enable register ? offset 48h................................................................................... 85 7.5.30 arbiter mode register ? offset 48h...................................................................................... 86 7.5.31 arbiter priority regist er ? offset 48h ................................................................................ 87 7.5.32 secondary cache line size register ? offs et 4ch .......................................................... 87 7.5.33 secondary latency time re gister ? offset 4ch............................................................... 88 7.5.34 secondary header type register ? offset 4ch ................................................................ 88 7.5.35 secondary csr and memory 0 base address register ? offset 50h.......................... 88 7.5.36 secondary csr i/o base address register ? offset 54h ................................................. 89 7.5.37 upstream i/o or memory 1 base address register ? offset 58h................................. 89 7.5.38 upstream memory 2 base address register ? offset 5ch............................................. 89 7.5.39 upstream memory 3 base address register ? offset 60h ............................................. 90 7.5.40 upstream memory 3 upper base address register ? offset 64h................................ 91 7.5.41 express transmitter/receiver register ? offset 68h.................................................... 91 7.5.42 memory address forwarding cont rol register ? offset 68h .................................. 92 7.5.43 upstream memory write fragment control register ? offset 68h ....................... 93
pi7c9x110 pcie-to-pci reversible bridge page 8 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.44 subsystem vendor id register ? offset 6ch ...................................................................... 93 7.5.45 subsystem id register ? offset 6ch....................................................................................... 93 7.5.46 eeprom autoload control/status register ? offset 70h........................................... 93 7.5.47 reserved register ? offset 74h............................................................................................... 94 7.5.48 bridge control and status register ? offs et 78h ......................................................... 94 7.5.49 gpio data and control register ? of fset 78h.................................................................. 95 7.5.50 secondary interrupt line re gister ? offset 7ch ........................................................... 95 7.5.51 secondary interrupt pin register ? offset 7ch.............................................................. 95 7.5.52 secondary minimum grant re gister ? offset 7ch .......................................................... 95 7.5.53 secondary maximum latency timer register ? offset 7ch......................................... 95 7.5.54 capability id regist er ? offset 80h ...................................................................................... 96 7.5.55 next capability pointer register ? offset 80h ................................................................ 96 7.5.56 secondary status register ? offset 80h............................................................................ 96 7.5.57 bridge status register ? offset 84h .................................................................................... 97 7.5.58 upstream split transaction register ? offset 88h ........................................................ 98 7.5.59 downstream split transaction register ? offset 8ch ................................................. 98 7.5.60 power management id reg ister ? offs et 90h.................................................................... 98 7.5.61 next capability pointer register ? offset 90h ................................................................ 99 7.5.62 power management capability register ? offset 90h .................................................. 99 7.5.63 power management control and status register ? offset 94h .............................. 99 7.5.64 pci-to-pci support extension re gister ? offs et 94h ................................................... 100 7.5.65 downstream memory 0 translated ba se register ? offset 98h .............................. 100 7.5.66 downstream memory 0 setup re gister ? offs et 9ch ................................................... 100 7.5.67 capability id register ? offset a0h..................................................................................... 101 7.5.68 next pointer register ? offset a0h..................................................................................... 102 7.5.69 slot number register ? offset a0h ..................................................................................... 102 7.5.70 chassis number register ? offset a0h ............................................................................... 102 7.5.71 secondary clock and clkrun cont rol register ? offset a4h............................... 102 7.5.72 donwstream i/o or memory 1 translated base register ? offset a8h ................. 103 7.5.73 dowstream i/o or memory 1 setu p register ? offs et ach ......................................... 104 7.5.74 pci express capability id regi ster ? offset b0h ............................................................ 104 7.5.75 next capability pointer re gister ? offset b0h .............................................................. 104 7.5.76 pci express capability regis ter ? offset b0h ................................................................. 104 7.5.77 device capability regist er ? offset b4h........................................................................... 105 7.5.78 device control regist er ? offset b8h............................................................................... 106 7.5.79 device status register ? offset b8h................................................................................... 106 7.5.80 link capability register ? offset bch ............................................................................... 107 7.5.81 link control register ? offset c0h.................................................................................... 107 7.5.82 link status register ? offset c0h........................................................................................ 109 7.5.83 slot capability regist er ? offset c4h ............................................................................... 109 7.5.84 slot control register ? offset c8h ................................................................................... 109 7.5.85 slot status register ? offset c8h ....................................................................................... 110 7.5.86 xpip configuration register 0 ? offset cch................................................................... 110 7.5.87 xpip configuration register 1 ? offset d0h ................................................................... 110 7.5.88 xpip configuration register 2 ? offset d4h ................................................................... 110 7.5.89 capability id register ? offset d8h .................................................................................... 111 7.5.90 next pointer register ? offset d8h .................................................................................... 111 7.5.91 vpd register ? offset d8h ...................................................................................................... .111 7.5.92 vpd data register ? offset dch............................................................................................ 111 7.5.93 upstream memory 0 translated base register ? offset e0h .................................... 111 7.5.94 upstream memory 0 setup register ? offset e4h .......................................................... 112 7.5.95 upstream i/o or memory 1 translated base register ? offset e8h ....................... 112
pi7c9x110 pcie-to-pci reversible bridge page 9 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.96 upstream i/o or memory 1 setup register ? offset ech............................................. 112 7.5.97 message signaled interrupt s id register ? f0h............................................................. 114 7.5.98 next capabilities point er register ? f0h.......................................................................... 114 7.5.99 message control regist er ? offset f0h ........................................................................... 114 7.5.100 message address regist er ? offset f4h ............................................................................ 114 7.5.101 message upper address regi ster ? offset f8h............................................................... 114 7.5.102 message data register ? offset fch................................................................................... 114 7.5.103 advance error reporting capability id register ? offset 100h ............................ 115 7.5.104 advance error reporting capability ver sion register ? offset 100h ................ 115 7.5.105 next capability offset reg ister ? offset 100h .............................................................. 115 7.5.106 uncorrectable error status re gister ? offs et 104h ................................................. 115 7.5.107 uncorrectable error mask re gister ? offset 108h .................................................... 115 7.5.108 uncorrectable error severity re gister ? offset 10ch............................................. 116 7.5.109 correctable error status re gister ? offset 110h....................................................... 116 7.5.110 correctable error mask regi ster ? offset 114h .......................................................... 116 7.5.111 advanced error capabilities and control register ? offset 118h...................... 117 7.5.112 header log register 1 ? offset 11ch .................................................................................. 117 7.5.113 header log register 2 ? offset 120h................................................................................... 117 7.5.114 header log register 3 ? offset 124h................................................................................... 117 7.5.115 header log register 4 ? offset 128h................................................................................... 117 7.5.116 secondary uncorrectable error status register ? offset 12ch ......................... 117 7.5.117 secondary uncorrectable error ma sk register ? offset 130h ............................. 118 7.5.118 secondary uncorrectable error severity register ? offset 134h ...................... 118 7.5.119 secondary error capability and control register ? offset 138h........................ 119 7.5.120 secondary header log register ? offset 13ch ? 148h.................................................. 119 7.5.121 reserved register ? offset 14ch .......................................................................................... 119 7.5.122 vc capability id regist er ? offset 150h ............................................................................. 119 7.5.123 vc capability version regis ter ? offset 150h ................................................................. 119 7.5.124 next capability offset reg ister ? offset 150h .............................................................. 120 7.5.125 port vc capability regist er 1 ? offset 154h .................................................................... 120 7.5.126 port vc capability regist er 2 ? offset 158h .................................................................... 120 7.5.127 port vc control regist er ? offset 15ch........................................................................... 120 7.5.128 port vc status regist er ? offset 15ch............................................................................... 120 7.5.129 vc0 resource capability regi ster ? offset 160h ........................................................... 120 7.5.130 vc0 resource control regis ter ? offset 164h ............................................................... 120 7.5.131 vc0 resource status regi ster ? offset 168h ................................................................... 121 7.5.132 reserved registers ? offs et 16ch ? 300h ............................................................................ 121 7.5.133 extra gpi/gpo data and control register ? offset 304h........................................... 121 7.5.134 reserved registers ? of fset 308h ? 30ch ............................................................................ 121 7.5.135 replay and acknowledge latency timers ? offset 310h ........................................... 121 7.5.136 reserved registers ? of fset 314h ? ffch ........................................................................... 121 7.6 control and status registers fo r non-transparent bridge mode 122 7.6.1 reserved registers ? offs et 000h to 004h.......................................................................... 122 7.6.2 downstream memory 2 translated ba se register ? offset 008h ............................ 122 7.6.3 downstream memory 2 setup re gister ? offset 00ch.................................................. 122 7.6.4 downstream memory 3 translated ba se register ? offset 010h ............................ 122 7.6.5 downstream memory 3 setup re gister ? offs et 014h .................................................. 123 7.6.6 downstream memory 3 upper 32-bit setup register ? offset 018h ........................ 123 7.6.7 reserved registers ? offs et 01ch to 030h ......................................................................... 123 7.6.8 upstream memory 3 setup register ? offset 34h........................................................... 123 7.6.9 upstream memory 3 upper 32-bit se tup register ? o ffset 038h............................... 124
pi7c9x110 pcie-to-pci reversible bridge page 10 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.10 reserved registers ? offs et 03ch to 04ch ........................................................................ 124 7.6.11 lookup table offset ? offset 050h ..................................................................................... 124 7.6.12 lookup table data ? offset 054h.......................................................................................... 124 7.6.13 upstream page boundary irq 0 request register ? offset 058h ............................ 125 7.6.14 upstream page boundary irq 1 request register ? offset 05ch............................ 125 7.6.15 upstream page boundary irq 0 mask register ? offset 060h ................................... 126 7.6.16 upstream page boundary irq 1 mask register ? offset 064h ................................... 126 7.6.17 reserved register ? offset 068c .......................................................................................... 126 7.6.18 primary clear irq regist er ? offset 070h......................................................................... 126 7.6.19 secondary clear irq regist er ? offset 070h................................................................... 126 7.6.20 primary set irq register ? offset 074h .............................................................................. 127 7.6.21 secondary set irq regist er ? offset 074h ........................................................................ 127 7.6.22 primary clear irq mask reg ister ? offs et 078h ............................................................. 127 7.6.23 secondary clear irq mask regi ster ? offset 078h ....................................................... 127 7.6.24 primary set irq mask register ? offset 07ch .................................................................. 128 7.6.25 secondary set irq mask reg ister ? offset 07ch ............................................................ 128 7.6.26 reserved registers ? offs et 080h to 09ch ......................................................................... 128 7.6.27 scratchpad 0 register ? offset 0a0h.................................................................................. 128 7.6.28 scratchpad 1 register ? offset 0a4h.................................................................................. 128 7.6.29 scratchpad 2 register ? offset 0a8h.................................................................................. 129 7.6.30 scratchpad 3 register ? offset 0ach ................................................................................. 129 7.6.31 scratchpad 4 register ? offset 0b0h.................................................................................. 129 7.6.32 scratchpad 5 register ? offset 0b4h.................................................................................. 129 7.6.33 scratchpad 6 register ? offset 0b8h.................................................................................. 129 7.6.34 scratchpad 7 register ? offset 0bch ................................................................................. 130 7.6.35 reserved registers ? offs et 0c0h to 0fch........................................................................ 130 7.6.36 lookup table registers ? offset 100h to 1fch ............................................................... 130 7.6.37 reserved registers ? offs et 200h to ffch ........................................................................ 130 8 gpio pins and sm bus address..................................................................................... 131 9 clock scheme ................................................................................................................... .. 132 10 interrupts..................................................................................................................... .... 132 11 eeprom (i2c) interface and system management bus ........................... 132 11.1 eeprom (i2c) interface .................................................................................................... ...................... 133 11.2 system ma nagement bus..................................................................................................... ................ 133 12 hot plug operation .................................................................................................... 133 13 reset scheme................................................................................................................... 133 14 ieee 1149.1 compatible jtag controller ....................................................... 134 14.1 instruct ion register ...................................................................................................... ...................... 134 14.2 bypass register........................................................................................................... ............................. 135 14.3 device id register........................................................................................................ ........................... 135 14.4 boundary scan register.................................................................................................... ................. 135 14.5 jtag boundary scan register order ......................................................................................... .. 135 15 power management .................................................................................................... 138 16 electrical and timing specifications........................................................... 140
pi7c9x110 pcie-to-pci reversible bridge page 11 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 16.1 absolute ma ximum ratings .................................................................................................. ............ 140 16.2 dc specifications......................................................................................................... ............................ 140 16.3 ac specifications......................................................................................................... ............................ 141 17 package information................................................................................................ 142 18 ordering information.............................................................................................. 143
pi7c9x110 pcie-to-pci reversible bridge page 12 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 table of figures f igure 1-1 pi7c9x110 t opology ............................................................................................................................... ....... 14 f igure 4-1 f orward and n on - transparent b ridge m ode ............................................................................................ 22 f igure 4-2 r everse and t ransparent b ridge m ode ...................................................................................................... 23 f igure 16-1 pci signal timing conditions ..................................................................................................................... 141 f igure 17-1 t op view drawing ............................................................................................................................... .......... 142 f igure 17-2 b ottom view drawing ............................................................................................................................... ... 142 f igure 17-3 p ackage outline drawing ........................................................................................................................... 143 list of tables t able 2-1 p in a ssignments ............................................................................................................................... .................. 19 t able 3-1 m ode s election ............................................................................................................................... .................. 21 t able 3-2 p in s trapping ............................................................................................................................... ....................... 21 t able 5-1 n on - transparent r egisters ............................................................................................................................ 25 t able 6-1 tlp f ormat ............................................................................................................................... ......................... 26 t able 7-1 c onfiguration r egister m ap (00 h ? ff h ) ...................................................................................................... 27 t able 7-2 pci e xpress e xtended c apability r egister m ap (100 h ? fff h ) ................................................................. 30 t able 7-3 c ontrol and s tatus r egister (csr) m ap (000 h ? fff h ) ............................................................................. 31 t able 8-1 sm b us d evice id s trapping .......................................................................................................................... 131 t able 10-1 pci e interrupt message to pci interrupt mapping in reverse bridge mode ......................................... 132 t able 10-2 pci interrupt to pci e interrupt message mapping in forward bridge mode ....................................... 132 t able 14-1 i nstruction register codes ......................................................................................................................... 135 t able 14-2 jtag device id register .............................................................................................................................. 1 35 t able 14-3 jtag boundary scar register definition ................................................................................................. 135 t able 16-1 a bsolute maximum ratings ......................................................................................................................... 140 t able 16-2 dc electrical characteristics .................................................................................................................. 140 t able 16-3 pci bus timing parameters .......................................................................................................................... 141
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pi7c9x110 pcie-to-pci reversible bridge page 14 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 1 introduction pi7c9x110 is a pcie-to-pci bridge. pi7c9x110 is compliant with the pci express base specification, revision 1.0a, the pci express card electromechanical specification , revision 1.0a, the pci local bus specification, revision 3.0 and pci express to pci bridge specification , revision 1.0. pi7c9x110 supports transparent and non-transparent mode of operations. also, pi7c9x110b supports forward and reverse bridging. in forward bridge mode, pi7c9x110 has an x1 pci express upstream port and a 32-bit pci downstream port. the 32-bit pci downstream port is 66mhz capable (see figure 1-1). in reverse bridge mode, pi7c9x110 has a 32-bit pci upstream port and an x1 pci express downstream port. pi7c9x110 configuration registers are backward compatible with existing pci bridge software and firmware . no modification of pci br idge software and firmware is needed for the original operation. figure 1-1 pi7c9x110 topology 1.1 pci express features ? compliant with pci express base specification, revision 1.0a ? compliant with pci express card electrom echanical specification, revision 1.0a ? compliant with pci express to pci bridge specification, revision 1.0 ? physical layer interface (x1 link with 2.5gb/s data rate) ? lane polarity toggle ? virtual isochronous support (upstream tc1-7 generation, downstream tc1-7 mapping) ? aspm support ? beacon support ? crc (16-bit), lcrc (32-bit) ? ecrc and advanced error reporting ? prbs (pseudo random bit sequencing) generator/checker for chip testing pi7c9x110 x1 pci express port tx rx pci 32bit / 66mhz bus pci device pci device pci device pci device pci device pci device pci device pci device
pi7c9x110 pcie-to-pci reversible bridge page 15 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 ? maximum payload size to 512 bytes 1.2 pci features ? compliant with pci local bus specification, revision 3.0 ? compliant with pci-to-pci bridge architecture specification, revision 1.2 ? compliant with pci bus pm inte rface specification, revision 1.1 ? compliant with pci hot-plug specification, revision 1.1 ? compliant with pci mobile design guide, version 1.1 ? pme support ? 3.3v pci signaling with 5v i/o tolerance ? provides two level arbitration support for eight pci bus masters ? 16-bit address decode for vga ? subsystem vendor and subsystem device ids support ? capable of supporting minimum pci frequency of 10mhz ? pci int interrupt or msi function support 1.3 general features ? compliant with advanced configuration and po wer interface specification (acpi), revision 2.0b ? compliant with system management (sm) bus, version 2.0 ? forward bridging (pci express as primary bus, pci as secondary bus) ? reverse bridging (pci as primary bus, pci express as secondary bus) ? transparent mode support ? non-transparent mode support ? gpio support (4 bi-directional pins) ? power management (including acpi, clkrun_l, pci_pm) ? masquerade mode (pre-loadable vendor, device, and revision ids) ? eeprom (i2c) interface ? sm bus interface ? auxiliary powers (vaux, vd daux, vddcaux) support ? power consumption at about 1.0 watt in typical condition ? extended commercial/industrial temperature range (-40c to 85c)
pi7c9x110 pcie-to-pci reversible bridge page 16 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 2 pin definitions 2.1 signal types type of signal - descriptions b bi-directional i input iu input with pull-up id input with pull-down iod bi-directional with open drain output od open drain output o output p power g ground 2.2 pci express signals name pin assignment type description refclkp refclkn e3, e2 i reference clock inputs: connect to external 100mhz differential clock. these signals require ac coupled with 0.1uf capacitors. rp rn g4, h4 i pci express data inputs: differential data receiver input signals tp tn g1, f1 o pci express data outputs: differential data transmitter output signals rref h3 i resistor reference: it is used to connect an extern al resistor (2.1k ohm +/- 1%) to vss to provide a reference current for the driver and equalization circuit. perst_l l3 i pci express fundamental reset: pi7c9x110b uses this reset to initialize the internal state machines. 2.3 pci signals name pin assignment type description ad [31:0] b3, a4, b4, d4, a5, c5, d5, b6, a7, b7, d7, a8, c8, d8, b9, c9, c12, d14, d12, d11, e13, f14, f13, f11, g12, g11, h13, h12, j14, j13, j11, k14 b address / data: multiplexed address and data bus. address phase is aligned with first clock of frame_l assertion. data phase is aligned with irdy_l or trdy_l assertion. data is transferred on rising edges of fbclkin when both irdy_l and trdy_l are asserted. during bus idle (both frame_l and irdy_l are de- asserted), pi7c9x110b drives ad to a valid logic level when arbiter is parking to pi7c9x110b on pci bus. cbe [3:0] c6, a10, c14, g14 b command / byte enables (active low): multiplexed command at address phase and byte enable at data phase. during a ddress phase, the initiator drives commands on cbe [3:0] signals to start the transaction. if the command is a write transaction, the initiator will drive the byte enables during data phase. otherwise, the target will drive the byte enables during data phase. duri ng bus idle, pi7c9x110b drives cbe [3:0] signals to a valid logic level when arb iter is parking to pi7c9x110b on pci bus. par b13 b parity bit: parity bit is an even parity (i.e. even number of 1?s), which generates based on the values of ad [31:0], cbe [3:0]. if pi7c9x110b is an initiator with a write transaction, pi7c9x110b will tri-state par. if pi7c9x110b is a target and a write transaction, pi7c9x110b will drive pa r one clock after the address or data phase. if pi7c9x110b is a target and a read transaction, pi7c9x110b will drive par one clock after the address phase and tr i-state par during data phases. par is tri-stated one cycle after the ad lines ar e tri-stated. during bus idle, pi7c9x110b drives par to a valid logic level when ar biter is parking to pi7c9x110b on pci bus. frame_l b10 b frame (active low): driven by the initiator of a transaction to indicate the beginning and duration an access. the de-a ssertion of frame_l indicates the final data phase signaled by the initiator in burst transfers. before being tri-stated, it is driven to a de-asserted state for one cycle.
pi7c9x110 pcie-to-pci reversible bridge page 17 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 name pin assignment type description irdy_l d10 b irdy (active low): driven by the initia tor of a transaction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de- asserted state for one cycle. trdy_l a11 b trdy (active low): driven by the target of a tran saction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase . before tri-stated, it is driven to a de- asserted state for one cycle. devsel_l b11 b device select (active low): asserted by the target indicating that the device is accepting the transaction. as a master, pi 7c9x110 waits for the assertion of this signal within 5 cycles of frame_l asser tion; otherwise, terminate with master abort. before tri-stated, it is driven to a de-asserted state for one cycle. stop_l a12 b stop (active low): asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri-st ated, it is driven to a de- asserted state for one cycle. lock_l a13 b lock (active low): asserted by the initiator for multiple transactions to complete. pi7c9x110b does not support any upstream lock transaction. idsel n14 i initialization device select: used as a chip select line for type 0 configuration access to bridge?s configuration space. perr_l a14 b parity error (active low): asserted when a data parity error is detected for data received on the pci bus interface. before bei ng tri-stated, it is driven to a de-asserted state for one cycle. serr_l b14 iod system error (active low): can be driven low by any device to indicate a system error condition. if serr control is enabled, pi7c9x110b will drive this pin on: address parity error posted write data par ity error on target bus master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout errors reported from pci express port (advanced error reporting) in transparent mode. this signal is an open drain buffer that requi res an external pull-up resistor for proper operation. req_l [7:0] p2, p1, n3, n2, n1, m3, m2, m1 i request (active low): req_l?s are asserted by bus master devices to request for transactions on the pci bus. the master de vices de-assert req_ls for at least 2 pci clock cycles before asserting them again. if external arbiter is selected (cfn_l=1), req_l [0] will be the bus grant input to pi7c9x110. also, req_l [5:2] will become the gpi [3:0]. gnt_l [7:0] n6, p6, p5, n5, m5, l5, n4, m4 o grant (active low): pi7c9x110 asserts gnt_ls to release pci bus control to bus master devices. during idle and all gnt_ls are de-asserted and arbiter is parking to pi7c9x110, pi7c9x110 will driv e ad, cbe, and par to valid logic levels. if external arbiter is select ed (cfn_l=1), gnt_l [0] will be the bus request from pi7c9x110 to external arbiter. also, gn t_l [5:2] will become the gpo [3:0]. clkout [8:0] n12, p12, n11, l10, m10, p10, l9, n9, p9 o pci clock outputs: pci clock outputs are derived from the clkin and provide clocking signals to external pci devices. reset_l n7 b reset_l (active low): when reset_l active, all pci signals should be asynchronously tri-stated. inta_l intb_l intc_l intd_l p3 m6 p13 n13 iod interrupt: signals are asserted to request an interrupt. after asserted, it can be cleared by the device driver. inta_l, intb_l, intc_l, intd_l signals are inputs and asynchronous to the clock in the forward mode. in reverse mode, inta_l, intb_l, intc_l, and intd_l are open dr ain buffers for sending interrupts to the host interrupt controller. fbclkin c2 i feedback clock input: it connects to one of the clkout [8:0] output signals and provides internal clocking to pi7c9x110 pci bus interface. clkin p7 i pci clock input: pci clock input signal connects to an external clock source. pi7c9x110 supports various pci frequency from 10mhz to 66mhz. the pci clock outputs clkout [8:0] pins ar e derived from clkin input.
pi7c9x110 pcie-to-pci reversible bridge page 18 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 2.4 mode select and strapping signals name pin assignment type description tm2 k3 i mode select 2: tm2 is a strapping pin. when tm2 is strapped low for normal operations and strapped high fo r testing functions. see ta ble 3-1 for mode selection and 3-2 for strapping control for details. tm1 c1 i mode select 1: mode selection pin to select eeprom or sm bus. tm1=0 for eeprom (i2c) support and tm1=1 for sm bus support. tm1 is also a strapping pin. see table 3-1 mode selecti on and 3-2 for strapping control. tm0 d1 i mode select 0: mode selection pin to select transparent or non-transparent mode. tm0=0 for transparent bridge function m ode and tm0=1 for non-transparent bridge function mode. tm0 is also a strapping pin. see table 3-1 for mode selection and 3-2 for strapping control. msk_in p14 i mask input for clkout: msk_in is used by pi7c9x110 to enable or disable the clock outputs. msk_in is also a strapping pi n. when it is strapped to high, hot-plug is enabled. see table 3-2 for strapping control. revrsb m12 i forward or reverse bridging pin: revrsb pin controls the forward (revrsb=0) or reverse (revrsb=1) bridge mode of pi7c9x110. this pin is also a strapping pin. see table 3-1 for mode selection. cfn_l m7 id bus central function control pin (active low): to enable the in ternal arbiter, cfn_l pin should be tied low. when it?s tied high, an external arbiter is required to arbitrate the bus. in exte rnal arbiter mode, req_l [0] is re-configured to be the secondary bus grant input, and gnt_l [0] is reconfigured to be the secondary bus request output. also, req_l [5:2] and gnt_l [5:2] become gpi [3:0] and gpo [3:0] respectively if external arbiter is selected. cfn_l has a weak internal pull-down resistor. see table 3-1 for mode selection. 2.5 jtag boundary scan signals name pin assignment type description tck l14 iu test clock: tck is the test clock to synchr onize the state information and data on the pci bus side of pi7c9x110 during boundary scan operation. tms l13 iu test mode select: tms controls the state of the test access port (tap) controller. tdo m13 o test data output: tdo is the test data output and connects to the end of the jtag scan chain. tdi m14 iu test data input: tdi is the test data input and connects to the beginning of the jtag scan chain. it allows the test instructi ons and data to be serially shifted into the pci side of pi7c9x110. trst_l k11 iu test reset (active low): trst_l is the test reset to initialize the test access port (tap) controller. 2.6 miscellaneous signals name pin assignment type description gpio [3:0] l7, p8, m8, l8 b general purpose i/o data pins: the 4 general-purpose signals are programmable as either input-only or bi-directional signals by writing the gpio output enable control register in the configuration space. see chapter 8 for more information. smbclk / scl a2 b smbus / eeprom clock pin: when eeprom (i2c) interface is selected (tm1=0), this pin is an output of scl cl ock and connected to eeprom clock input. when smbus interface is select ed (tm1=1), this pin is an input for the clock of smbus. smbdata / sda a1 b/iod smbus / eeprom data pin: data interface pin to eerpom or smbus. when eeprom (i2c) interface is selected (tm1=0), this pin is a bi-directional signal. when smbus interface is selected (tm1=1 ), this pin is an open drain signal. pme_l a3 b power management event pin: power management event signal is asserted to request a change in the device or link power state. clkrun_l d3 b clock run pin (active low): the clock run signal, for mobile environment, is asserted and de-asserted to indicate the status of the pci clock.
pi7c9x110 pcie-to-pci reversible bridge page 19 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 name pin assignment type description reserved 0 b1 i reserved 0 pin: for normal pci operation, reserved 0 pin is tied to ground with a capacitor (0.1uf) in parallel. reserved 1 d2 o reserved 1 pull-up driver: don?t care. 2.7 power and ground pins name pin assignment type description vdda j3, g3 p analog voltage supply for pci express interface: connect to the 1.8v power supply. vddp f3, f4, k2 p digital voltage supply for pci express interface: connect to the 1.8v power supply. vddaux f2 p auxiliary voltage supply for pci express interface: connect to the 1.8v power supply. vtt g2, k1 p termination supply voltage for pci express interface: connect to the 1.8v power supply. vdda_pll j4 p analog voltage supply for pll at pci interface: connect to the 1.8v power supply. vddc l1, n8, l11, l12, b12, c10, e4 p core supply voltage: connect to the 1.8v power supply. vddcaux l2 p auxiliary core supply voltage: connect to the 1.8v power supply. vd33 l4, n10, m11, k12, j12, h14, f12, e11, d13, a9, c7, a6, c4 p i/o supply voltage for pci interface: connect to the 3.3v power supply for pci i/o buffers. vaux b2 p auxiliary i/o supply volt age for pci interface: connect to the 3.3v power supply. vss e1, h1, h2, j2, j1, k4, p4, l6, m9, p11, k13, h11, g13, e12, e14, c13, c11, d9, b8, d6, b5, c3 p ground: connect to ground. vdda j3, g3 p analog voltage supply for pci express interface: connect to the 1.8v power supply. 2.8 pin assignments table 2-1 pin assignments pin name pin name pin name pin name a1 smbdat / sda c13 vss h1 vss m3 req_l[2]/gpi[0] a2 smbclk / scl c14 cbe [1] h2 vss m4 gnt_l [0] a3 pme_l d1 tm0 h3 rref m5 gnt_l[3]/gpo[1] a4 ad [30] d2 reserved 1 h4 rn m6 intb_l a5 ad [27] d3 clkrun_l h11 vss m7 cfn_l a6 vd33 d4 ad [28] h12 ad [4] m8 gpio [1] a7 ad [23] d5 ad [25] h13 ad [5] m9 vss a8 ad [20] d6 vss h14 vd33 m10 clkout [4] a9 vd33 d7 ad [21] j1 vss m11 vd33 a10 cbe [2] d8 ad [18] j2 vss m12 revrsb a11 trdy_l d9 vss j3 vdda m13 tdo a12 stop_l d10 irdy_l j4 vdda_pll m14 tdi a13 lock_l d11 ad [12] j11 ad [1] n1 req_l[3] / gpi[1] a14 perr_l d12 ad [13] j12 vd33 n2 req_l[4] / gpi[2] b1 reserved 0 d13 vd33 j13 ad [2] n3 req_l[5] / gpi[3] b2 vaux d14 ad [14] j14 ad [3] n4 gnt_l [1] b3 ad [31] e1 vss k1 vtt n5 gnt_l[4]/gpo[2] b4 ad [29] e2 refclkn k2 vddp n6 gnt_l [7] b5 vss e3 refclkp k3 tm2 n7 reset_l b6 ad [24] e4 vddc k4 vss n8 vddc b7 ad [22] e11 vd33 k11 trst_l n9 clkout [1]
pi7c9x110 pcie-to-pci reversible bridge page 20 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 pin name pin name pin name pin name b8 vss e12 vss k12 vd33 n10 vd33 b9 ad [17] e13 ad [11] k13 vss n11 clkout [6] b10 frame_l e14 vss k14 ad [0] n12 clkout [8] b11 devsel_l f1 tn l1 vddc n13 intd_l b12 vddc f2 vddaux l2 vddcaux n14 idsel b13 par f3 vddp l3 perst_l p1 req_l [6] b14 serr_l f4 vddp l4 vd33 p2 req_l [7] c1 tm1 f11 ad [8] l5 gnt_l[2]/gpo[0] p3 inta_l c2 fbclkin f12 vd33 l6 vss p4 vss c3 vss f13 ad [9] l7 gpio [3] p5 gnt_l[5]/gpo[3] c4 vd33 f14 ad [10] l8 gpio [0] p6 gnt_l [6] c5 ad [26] g1 tp l9 clkout [2] p7 clkin c6 cbe [3] g2 vtt l10 clkout [5] p8 gpio [2] c7 vd33 g3 vdda l11 vddc p9 clkout [0] c8 ad [19] g4 rp l12 vddc p10 clkout [3] c9 ad [16] g11 ad [6] l13 tms p11 vss c10 vddc g12 ad [7] l14 tck p12 clkkout [7] c11 vss g13 vss m1 req_l [0] p13 intc_l c12 ad [15] g14 cbe [0] m2 req_l [1] p14 msk_in
pi7c9x110 pcie-to-pci reversible bridge page 21 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 3 mode selection and pin strapping 3.1 functional mode selection if tm2 is strapped to low, pi7c9x110 uses tm1, tm0, cfn_l, and revrsb pins to select different modes of operations. these four input signals are required to be stable during normal operation. one of the sixteen combinations of normal operation can be selected by setting the logic values for the four mode select pins. for example, if the logic values are low for all four (tm1, tm0, cfn_l, and revrsb) pins, the normal operation will have eeprom (i2c) support in transparent mode with internal arbiter in forward bridge mode. the designated operation with respect to the values of the tm1, tm0, cfn_l, and revrsb pins are defined on table 3-1: table 3-1 mode selection tm2 strapped tm1 tm0 cfn_l revrsb functional mode 0 0 x x x eeprom (i2c) support 0 1 x x x sm bus support 0 x 0 x x transparent mode 0 x 1 x x non-transparent mode 0 x x 0 x internal arbiter 0 x x 1 x external arbiter 0 x x x 0 forward bridge mode 0 x x x 1 reverse bridge mode 3.2 pin strapping if tm2 is strapped to high, pi7c9x110 uses tm1, tm0, and msk_in as strapping pins. the strapping functions are listed in table 3-2 to show the states of operations during the pci express perst_l de-assertion transition in forward bridge mode or pci reset_l de-asse rtion transition in reverse bridge mode. table 3-2 pin strapping tm2 strapped tm1 strapped tm0 strapped msk_in strapped test functions 1 0 0 1 pll test 1 0 1 1 shorten initialization test with hot- plug enabled 1 1 0 1 functional loopback test 1 1 1 1 bridge test (prbs, iddq, etc.) 1 0 0 0 reserved 1 0 1 0 shorten initialization test with hot- plug disabled 1 1 0 0 reserved 1 1 1 0 reserved 4 forward and reverse bridging pi7c9x110 supports forward or reverse and transparent or non-transparent combination modes of operation. for example, when pi7c9x110 is operating in forward (revrsb=0) and non-transparent bridge mode (tm0=1) shown in figure 4-1, its pci express interface is connected to a root complex and its pci bus interface is connected to pci devices. another example, pi7c9x110 can be configured as a reverse (revrsb=1) and transparent (tm0=0) bridge shown in figure 4-2.
pi7c9x110 pcie-to-pci reversible bridge page 22 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 the non-transparent bridge feature of pi7c9x110 allows th e i/o processor to be isolat ed from the host processor and its memory map which avoiding memory address conflict when both host and i/o processors are needed side- by-side. pci based systems and peripherals are ubiquitous in the i/ o interconnect technology market today. it will be a tremendous effort to convert existing pci based products to be used in pci express systems. pi7c9x110 provides a solution to bridge existing pci based products to the latest pci express technology. figure 4-1 forward and non-transparent bridge mode in reverse (revrsb=1) and transparent (tm0=0) mode shown in figure 3-2, pi7c9x110 becomes a pci-to-pci express bridge that its pci bus interface is connected to the host chipset betw een and the pci express x1 link. it enables the legacy pci host systems to provide pci express capability. pi7c9x110 provides a solution to convert existing pci based designs to adapt quickly into pci express base platforms. existing pci based applications will not have to undergo a comp lete re-architecture in order to interface to pci express technology. pi7c9x110 fibre channel root complex fast ethernet scsi host processor system memory local processor local memory x1 link 32bit / 66mhz
pi7c9x110 pcie-to-pci reversible bridge page 23 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 figure 4-2 reverse and transparent bridge mode pi7c9x110 fibre channel chipset fast ethernet scsi host processor system memory 32bit / 66mhz x1 link
pi7c9x110 pcie-to-pci reversible bridge page 24 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 5 transparent and non- transparent bridging 5.1 transparent mode in transparent bridge mode, base class code of pi7c9x110 is set to be 06h (bridge device). the sub-class code is set to be 04h (pci-to-pci bridge). programming interface is 00h. hence, pi7c9x110 is not a subtractive decoding bridge. pi7c9x110 has type-1 configuration header if tm0 is set to 0 (transparent bridge mode). these configuration registers are the same as traditional tr ansparent pci-to-pci bridge. in fact, it is backward compatible to the software that supporting traditional tr ansparent pci-to-pci bridges. config uration registers can be accessed from several different ways. for pci express access, pci express configuration transaction is in forward bridge mode. for pci access, pci configuration cycle is mainly in re verse bridge mode. howeve r, pi7c9x110 allows pci configuration access in forward mode as secondary bus c onfiguration access. for i2c acc ess, i2c bus protocol is used with eeprom selected (tm1=0). for sm bus acce ss, sm bus protocol is us ed with sm bus selected (tm1=1). 5.2 non-transparent mode in non-transparent bridge mode, base class code of pi7c9x110 is set to be 06h (bridge device). the sub-class code is set to be 80h (other bridge). programming interface is 00h. hence, pi7c9x110 is not a subtractive decoding bridge. pi7c9x110 has type-0 configuration header if tm0 is set to 1 (non-transparent mode). the configuration registers are similar to a traditional pci device. however, there is one set of configuration regi sters for the primary interface and another set of configuration registers for the seconda ry interface. in addition, csrs (control and status registers) are implemented to support the memory or io transfers between the primary and secondary buses. the csrs are accessed through memory transaction access within the lowest memory range of 4k space (bit [64:12] are zeros). the non-transparent configuration registers can be accessed through several different ways (pci express, pci, i2c, and sm bus). for pci express and pci access, the type-0 configuration transacti ons need to be used. for i2c access, i2c bus protocol needs to be used through i2 c bus interface. for sm bu s access, sm bus protocol needs to be used through sm bus interface. the hard ware pins (a2 and a1) are shared for i2c and sm bus interface. if tm1=0, pin a2 and a1 will be scl and sd a for i2c interface respectively. if tm1=1, pin a2 and a1 will be smbclk and smbdata for sm bus interface respectively. in non-transparent bridge mode, pi7c9x110 supports four or three memory bars (base address registers) and one or two io bars (base address registers) depending on selection on the primary bus. also, pi7c9x110 supports four or three memory bars (b ase address registers) and one or tw o io bars (base address registers) depending on selection on the secondary bus. offset 10h is defined to be primary csr and downstream memory 0 bar. offset 14h is defined to be primary csr and downstream io bar. offset 18h is defined to be downstream memory 1 or io bar (selectable by csr setup register). offset 1ch is defined to be downstream memory 2 bar. offset 20h and 24h are defined to be downstream memory 3 lower bar and memory 3 upper bar respectively to support 64-bit decoding. the direct offset translation of address from primary to secondary bus will be done by substituting the original base address at primary with the downstream translation base address register values and keeping the lower address bits the same to form a new address for forward the transaction to secondary bus. for downstream memory 2, it uses direct address transla tion. there is no lookup table for downstream memory address translation.
pi7c9x110 pcie-to-pci reversible bridge page 25 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 offset 50h is defined to be secondary csr and upstream memory 0 bar. offset 54h is defined to be secondary csr and upstream io bar. offset 58h is defined to be upstream memory 1 or io bar (selectable by csr setup register offset e4h). offset 1ch is defined to be upstream memory 2 bar. offset 60h and 64h are defined to be upstream memory 3 lower bar and memory 3 upper bar respectively to support 64-bit decoding. the direct offset translation of address from secondary to primary bus will be done by substituting the original base address at secondary with the upstream translation base address register values and keeping the lower address bits the same to form a new address for forward the transaction to primary bus. for upstream memory 2, it uses lookup table address translation method which using the original base address as index to select a new address on the upstream memory 2 lookup table based on the page and window size defined. table 5-1 non-transparent registers non-transparent registers typical access primary csr and memory 0 bar configuration access offset 10h downstream memory 0 translated base configuration access offset 98h downstream memory 0 setup configuration access offset 9ch downstream i/o or memory 1 bar configuration access offset 18h downstream i/o or memory 1 translated base configuration access offset a8h downstream i/o or memory 1 setup configuration access offset ach downstream memory 2 bar configuration access offset 1fh downstream memory 2 translated base lower 4k i/o or memory access offset 008h downstream memory 2 setup lower 4k i/o or memory access offset 00ch downstream memory 3 bar configuration access offset 23h downstream memory 3 upper 32-bit bar configuration access offset 27h downstream memory 3 translated base lower 4k i/o or memory access offset 010h downstream memory 3 setup lower 4k i/o or memory access offset 014h downstream memory 3 upper 32-bit setup lower 4k i/o or memory access offset 018h secondary csr memory 0 bar configuration access offset 50h upstream memory 0 translated base configuration access offset e0h upstream memory 0 setup configuration access offset e4h secondary csr i/o bar configuration access offset 54h upstream i/o or memory 1 bar configuration access offset 58h upstream i/o or memory 1 translated base configuration access offset e8h upstream i/o or memory 1 setup configuration access offset ech upstream memory 2 bar configuration access offset 5fh upstream memory 2 lookup table offset lo wer 4k i/o or memory access offset 050h upstream memory 2 lookup table data lower 4k i/o or memory access offset 054h upstream memory 2 lookup table (64 32-bit entries) lower 4k i/o or memory access offset 100h to 1ffh upstream memory 3 bar configuration access offset 63h upstream memory 3 upper 32-bit bar configuration access offset 67h upstream memory 3 setup lower 4k i/o or memory access offset 34h upstream memory 3 upper 32-bit setup lower 4k i/o or memory access offset 38h
pi7c9x110 pcie-to-pci reversible bridge page 26 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 6 pci express functional overview 6.1 tlp structure pci express tlp (transaction layer packet) structure is co mprised of format, type, traf fic class, attributes, tlp digest, tlp poison, and length of data payload. there are four tlp formats defined in pi7c9x110 based on the states of fmt [1] and fmt [0] as shown on table 6-1. table 6-1 tlp format fmt [1] fmt [0] tlp format 0 0 3 double word, without data 0 1 4 double word, without data 1 0 3 double word, with data 1 1 4 double word, with data data payload of pi7c9x110 can range from 4 (1dw) to 256 (64dw) bytes. pi7c9x110 supports three tlp routing mechanisms. they are comprise d of address, id, and implicit routings. address routing is being used for memory and io requests. id based (bus, device, function numbers) routing is being used for configuration requests. implicit routing is being used for message routing. there are two message groups (baseline and advanced switching). the baseline message group contains intx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. the other is advanced switching support message group. the advanced switching support message contains data packet and signal packet messages. advanced switching is beyond the scope of pi7c9x110 implementation. the r [2:0] values of the "type" field will determine the destination of the message to be routed. all baseline messages must use the default traffic class zero (tc0). 6.2 virtual isochronous operation this section provides a summary of virtual isochronous operation supported by pi7c9x110. virtual isochronous support is disabled by default. virtua l isochronous feature can be turned on with setting bit [26] of offset 40h to one. control bits are designated for se lecting which traffic class (tc1-7) to be used for upstream (pci express-to- pci). pi7c9x110 accepts only tc0 p ackets of configuration, io, and me ssage packets for downstream (pci express-to-pci). if configuration, io and message packet s have traffic class other than tc0, pi7c9x110 will treat them as malformed packets. pi7c9x110 maps all downstream memory packets from pci express to pci transactions regardless the virtual isochronous operation is enabled or not. 7 configuration registers pi7c9x110 supports type-0 (non-transparent bridge mode) and type-1 (transparent bridge mode) configuration space headers and capability id of 01h (pci power mana gement) to 10h (pci expr ess capability structure). with pin revrsb = 0, device-port type (bit [7:4]) of cap ability register will be set to 7h (pci e xpress-to-pci bridge). when pin revrsb = 1, device-port type (bit [7:4]) of capability register will be set to 8h (pci-to-pci express bridge). pi7c9x110 supports pci express capabilitie s register structure with capability version set to 1h (bit [3:0] of offset 02h).
pi7c9x110 pcie-to-pci reversible bridge page 27 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 when pin tm0=0, pi7c9x110 will be in transparent bridge mode and the co nfiguration registers for transparent bridge should be used. when pin tm0=1, pi7c9x110 will be in non-transparent bridge mode and the configuration registers for non- transparent bridge should be used. 7.1 configuration register map pi7c9x110 supports capability pointer w ith (id=07h), pci power management (id=01h), pci bridge sub-system vendor id (id=0dh), pci express (id=10h), vital product data (id=03h), and message signaled interrupt (id=05h). slot identification (id=04h) is off by default and can be turned on through configuration programming. table 7-1 configuration register map (00h ? ffh) primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access 01h - 00h 01h ? 00h vendor id vendor id yes1 yes5 03h ? 02h 03h ? 02h device id device id yes1 yes5 05h ? 04h 45h ? 44h command register primary command register no yes 07h ? 06h 47h ? 46h primary status register primary status register no yes 0bh ? 08h 0bh ? 08h class code and revision id class code and revision id yes1 yes5 0ch 4ch cacheline size register primary cacheline size register - - 0dh 4dh primary latency timer primary latency timer no yes 0eh 4eh header type register header type register no yes 0fh 4fh reserved reserved - - 13h ? 10h 53h ? 50h reserved primary csr and memory 0 bar no yes 17h ? 14h 57h ? 54h reserved primary csr i/o bar no yes 18h 58h primary bus number register downstream i/o or memory 1 bar no yes 19h 59h secondary bus number register downstream i/o or memory 1 bar no yes 1ah 5ah subordinate bus number register downstream i/o or memory 1 bar no yes 1bh 5bh secondary latency timer downstream i/o or memory 1 bar no yes 1ch 5ch i/o base register downstream memory 2 bar no yes 1dh 5dh i/o limit register downstream memory 2 bar no yes 1fh ? 1eh 5fh ? 5eh secondary status register downstream memory 2 bar no yes 21h ? 20h 61h ? 60h memory base register downstream memory 3 bar no yes 23h ? 22h 63h ? 62h memory limit register downstream memory 3 bar no yes 25h ? 24h 65h ? 64h prefetchable memory base register downstream memory 3 upper 32-bit bar no yes
pi7c9x110 pcie-to-pci reversible bridge page 28 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access 27h ? 26h 67h - 66h prefetchable memory limit register downstream memory 3 upper 32-bit bar no yes 2bh ? 28h 2bh ? 28h prefetchable memory base upper 32-bit register no yes 2dh ? 2ch 2dh ? 2ch prefetchable memory limit upper 32-bit register subsystem vendor id yes2 yes5 2fh ? 2eh 2fh ? 2eh prefetchable memory limit upper 32-bit register subsystem id yes2 yes5 31h ? 30h 31h ? 30h i/o base upper 16-bit register reserved no yes 33h ? 32h 33h ? 32h i/o limit upper 16-bit register reserved no yes 34h 34h capability pointer capability pointer no yes 37h ? 35h 37h ? 35h reserved reserved no yes 3bh ? 38h 3bh ? 38h reserved reserved no yes 3ch 7ch interrupt line primary interrupt line no yes 3dh 7dh interrupt pin prim ary interrupt pin no yes 3eh 7eh bridge control primary min_gnt yes 3 yes 3 3fh 7fh bridge control primary max_lat yes 3 yes 3 41h ? 40h 41h ? 40h pci data buffering control pci data buffering control yes yes 43h ? 42h 43h ? 42h chip control 0 chip control 0 yes yes 45h ? 44h 05h ? 04h reserved secondary command register no yes 47h ? 46h 07h ? 06h reserved secondary status register no yes 4bh ? 48h 4bh ? 48h arbiter mode, enable, priority arbiter mode, enable, priority yes yes 4ch 0ch reserved secondary cacheline size register no yes 4dh 0dh reserved secondary status register no yes 4eh 0eh reserved header type no yes 4fh 0fh reserved reserved - - 53h ? 50h 13h ? 10h reserved secondary csr and memory 0 bar no yes 57h ? 54h 17h ? 14h reserved secondary csr i/o bar no yes 5bh ? 58h 1bh ? 18h reserved upstream i/o or memory 1 bar no yes 5fh ? 5ch 1fh ? 1ch reserved upstream memory 2 bar no yes 63h ? 60h 23h ? 20h reserved upstream memory 3 bar no yes 67h ? 64h 27h ? 24h reserved upstream memory 3 upper 32-bit bar no yes 69h ? 68h 69h ? 68h pci express tx and rx control pci express tx and rx control yes yes 6ah 6ah reserved memory address forwarding control yes 3 yes 3 6bh 6bh reserved reserved no yes 6dh ? 6ch 6dh ? 6ch reserved subsystem vendor id yes 2 yes 5 6fh ? 6eh 6fh ? 6eh reserved subsystem id yes 2 yes 5
pi7c9x110 pcie-to-pci reversible bridge page 29 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access 73h ? 70h 73h ? 70h eeprom (i2c) control and status register eeprom (i2c) control and status register no yes 77h ? 74h 77h ? 74h reserved reserved no yes 7bh ? 78h 7bh ? 78h gpio data and control (20 bits) gpio data and control (20 bits) no yes 7bh ? 78h 7bh ? 78h reserved (12 bits) bridge control and status (10 bits) no no 7bh ? 78h 7bh ? 78h reserved (12 bits) reserved (2 bits) no no 7ch 3ch reserved secondary interrupt line no yes 7dh 3dh reserved secondary interrupt pin no yes 7eh 3eh reserved secondary min_gnt yes 3 yes 3 7fh 3fh reserved secondary max_lat yes 3 yes 3 83h ? 80h 83h ? 80h capability capability no yes 87h ? 84h 87h ? 84h bridge stat us bridge status no yes 8bh ? 88h 8bh ? 88h upstream split transaction upstream split transaction no yes 8fh ? 8ch 8fh ? 8ch downstream split transaction downstream split transaction no yes 93h ? 90h 93h ? 90h power management capability power management capability yes yes 97h ? 94h 97h ? 94h power management control and status power management control and status no yes 9bh ? 98h 9bh ? 98h reserved downstream memory 0 translated base no yes 9fh ? 9ch 9fh ? 9ch reserved downstream memory 0 setup yes 3 yes 3 a3h ? a0h a3h ? a0h slot id capa bility slot id capability no yes a7h ? a4h a7h ? a 4h pci clock and clkrun control pci clock and clkrun control yes yes abh ? a8h abh ? a8h ssid and ssvid capability downstream i/o or memory 1 translated base no yes afh ? ach afh ? ach subsystem id and subsystem vendor id downstream i/o or memory 1 setup yes yes b3h ? b0h b3h ? b0h pci express capa bility pci express capability no yes b7h ? b4h b7h ? b4h device capability device capability yes yes bbh ? b8h bbh ? b8h device control and status device control and status no yes bfh ? bch bfh ? bch link capab ility link capability yes yes c3h ? c0h c3h ? c0h link control and status link control and status no yes c7h ? c4h c7h ? c4h slot capa bility slot capability no yes cbh ? c8h cbh ? c8h slot control and st atus slot control and status no yes cfh ? cch cfh ? cch xpip configuration register 0 xpip configuration register 0 yes yes d3h ? d0h d3h ? d0h xpip configuration register 1 xpip configuration register 1 yes yes d6h ? d4h d6h ? d4h xpip configuration register 2 xpip configuration register 2 yes yes d7h d7h reserved reserved yes yes dbh ? d8h dbh ? d8h vpd capability register vpd capability register no yes dfh ? dch dfh ? dch vpd data register vpd data register yes 4 yes
pi7c9x110 pcie-to-pci reversible bridge page 30 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access e3h ? e0h e3h ? e0h reserved upstream memory 0 translated base no yes e7h ? e4h e7h ? e4h reserved upstream memory 0 setup yes 3 yes 3 ebh ? e8h ebh ? e8h reserved upstream i/o or memory 1 translated base no yes efh ? ech efh ? ech reserved upstream i/o or memory 1 setup yes 3 yes 3 f3h ? f0h f3h ? f0h msi capability register msi capability register no yes f7h ? f4h f7h ? f4h message a ddress message address no yes fbh ? f8h fbh ? f8h message upper address message upper address no yes ffh ? fch ffh ? fch message date message date no yes note 1: when masquerade is enabled, it is pre-loadable. note 2: when both masquerade and non-trans parent mode are enabled, it is pre-loadable. note 3: when non-transparent mode is enabled, it is pre-loadable. note 4: the vpd data is read/write through i2c during vpd operation. note 5: read access only. 7.2 pci express extended capability register map pi7c9x110 also suppo rts pci express extended capab ilities with from 257-byte to 4096-byte space. the offset range is from 100h to fffh. the offset 100h is defined for advance error reporting (id=0001h). the offset 150h is defined for virtual channel (id=0002h). table 7-2 pci express extended capa bility register map (100h ? fffh) primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access 103h ? 100h 103h ? 100h advanced error reporting (aer) capability advanced error reporting (aer) capability no yes 5 107h ? 104h 107h ? 104h uncorrectable error status uncorrectable error status no yes 10bh ? 108h 10bh ? 108h uncorrectable error mask uncorrectable error mask no yes 10fh ? 10ch 10fh ? 10ch uncorrectable seve rity uncorrectable severity no yes 113h ? 110h 113h ? 110h correctable error status correctable error status no yes 117h ? 114h 117h ? 114h correctable error mask correctable error mask no yes 11bh ? 118h 11bh ? 118h aer control aer control no yes 12bh ? 11ch 12bh ? 11ch header log regi ster header log register no yes 12fh ? 12ch 12fh ? 12ch secondary uncorrectable error status secondary uncorrectable error status no yes
pi7c9x110 pcie-to-pci reversible bridge page 31 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 primary bus configuration access for both transparent and non-transparent mode, or secondary bus configuration access for transparent mode secondary bus configuration access for non-transparent mode only transparent mode (type1) non-transparent mode (type0) eeprom (i2c) access sm bus access 133h ? 130h 133h ? 130h secondary uncorrectable error mask secondary uncorrectable error mask no yes 137h ? 134h 137h ? 134h secondary uncorrectable severity secondary uncorrectable severity no yes 13bh ? 138h 13bh ? 138h secondary aer control secondary aer control no yes 14bh ? 13ch 14bh ? 13ch secondary header log register secondary header log register no yes 14fh ? 14ch 14fh ? 14ch reserved reserved no yes 153h ? 150h 153h ? 150h vc capability vc capability no yes 157h ? 154h 157h ? 154h port vc capability 1 port vc capability 1 no yes 15bh ? 158h 15bh ? 158h port vc capab ility 2 port vc capability 2 no yes 15fh ? 15ch 15fh ? 15ch port vc status and control port vc status and control no yes 163h ? 160h 163h ? 160h vc0 resource capability vc0 resource capability no yes 167h ? 164h 167h ? 164h vc0 resource control vc0 resource control no yes 16bh ? 168h 16bh ? 168h vc0 resource status vc0 resource status no yes 2ffh ? 170h 2ffh ? 170h reserved reserved no no 303h ? 300h 503h ? 500h reserved reserved no yes 307h ? 304h 507h ? 504h extended gpi/gpo data and control extended gpi/gpo data and control no yes 30fh ? 308h 50fh ? 508h reserved reserved no no 310h 510h replay and acknowledge latency timer replay and acknowledge latency timer yes yes 4ffh ? 314h 4ffh ? 314h reserved reserved no no 503h ? 500h 303h ? 300h reserved reserved no no 504h 304h reserved reserved no no 50fh ? 505h 30fh ? 305h reserved reserved no no 510h 310h reserved reserved no no fffh ? 514h fffh ? 514h reserved reserved no no note 5: read access only. 7.3 control and stat us register map table 7-3 control and status register (csr) map (000h ? fffh) pci express / pci memory offset sm bus offset register name reset value eeprom (i2c) access sm bus access 007h ? 000h 207h ? 200h reserved 0 no yes 00bh ? 008h 20bh ? 208h downstream memory 2 translated base xxxx_xxxxh no yes 00fh ? 00ch 20fh ? 20ch downstream memory 2 setup 0000_0000h yes yes 013h ? 010h 213h ? 210h downstream memory 3 translated base xxxx_xxxxh no yes 017h ? 014h 217h ? 214h downstream memory 3 setup 0000_0000h yes yes 01bh ? 018h 21bh ? 218h downstream memory 3 upper 32-bit setup 0000_0000h yes yes 02fh ? 01ch 22fh ? 21ch reserved 0 no yes
pi7c9x110 pcie-to-pci reversible bridge page 32 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 pci express / pci memory offset sm bus offset register name reset value eeprom (i2c) access sm bus access 033h ? 030h 233h ? 230h reserved x no yes 037h ? 034h 237h ? 234h upstream memory 3 setup 0000_0000h yes yes 03bh ? 038h 21bh ? 218h upstream memory 3 upper 32-bit setup 0000_0000h yes yes 04fh ? 03ch 24fh ? 23ch reserved 0 no yes 050h 250h lookup table offset register xxh no yes 053h ? 051h 253h ? 251h reserved 0 no yes 057h ? 054h 257h ? 254h lookup table data register xxxx_xxxxh no yes 05bh ? 058h 25bh ? 258h upstream page boundary irq 0 0000_0000h no yes 05fh ? 05ch 25fh ? 25ch upstream page boundary irq 1 0000_0000h no yes 063h ? 060h 263h ? 260h upstream page boundary irq mask 0 ffff_ffffh no yes 067h ? 064h 267h ? 264h upstream page boundary irq mask 1 ffff_ffffh no yes 06fh ? 068h 26fh ? 268h reserved 0 no yes 071h ? 070h 271h ? 270h primary clear irq register 0000h no yes 073h ? 072h 273h ? 272h secondary clear irq register 0000h no yes 075h ? 074h 275h ? 274h primary set irq register 0000h no yes 077h ? 076h 277h ? 276h secondary set irq register 0000h no yes 079h ? 078h 279h ? 278h primary clear irq mask register ffffh no yes 07bh ? 07ah 27bh ? 27ah secondary clear irq mask register ffffh no yes 07dh ? 07ch 27dh ? 27ch primary set irq mask register ffffh no yes 07fh ? 07eh 27fh ? 27eh secondary set irq mask register ffffh no yes 09fh ? 080h 29fh ? 280h reserved 0 no yes 0a3h ? 0a0h 2a3h ? 2a0h scratc h pad 0 xxxx_xxxxh no yes 0a7h ? 0a4h 2a7h ? 2a4h scratc h pad 1 xxxx_xxxxh no yes 0abh ? 0a8h 2abh ? 2a8h scratch pad 2 xxxx_xxxxh no yes 0afh ? 0ach 2afh ? 2ach scratch pad 3 xxxx_xxxxh no yes 0b3h ? 0b0h 2b3h ? 2b0h scratch pad 4 xxxx_xxxxh no yes 0b7h ? 0b4h 2b7h ? 2b4h scratch pad 5 xxxx_xxxxh no yes 0bbh ? 0b8h 2bbh ? 2b8h sc ratch pad 6 xxxx_xxxxh no yes 0bfh ? 0bch 2bch ? 2bfh scratch pad 7 xxxx_xxxxh no yes 0ffh ? 0c0h 2ffh ? 2c0h reserved 0 no yes 1ffh ? 100h 3ffh ? 300h upstream memory 2 lookup table 0 no yes fffh ? 200h 11ffh ? 400h reserved 0 no yes 7.4 pci configuration registers for transparent bridge mode the following section describes the conf iguration space when the device is in transparent mode. the descriptions for different register type are listed as follow: register type descriptions ro read only ros read only and sticky rw read/write
pi7c9x110 pcie-to-pci reversible bridge page 33 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 rwc read/write ?1? to clear rws read/write and sticky rwcs read/write ?1? to clear and sticky 7.4.1 vendor id ? offset 00h bit function type description 15:0 vendor id ro identifies pericom as the vendor of this device. returns 12d8h when read. 7.4.2 device id ? offset 00h bit function type description 31:16 device id ro identifies this device as the pi7c9x110. returns e110 when read. 7.4.3 command register ? offset 04h bit function type description 0 i/o space enable rw 0: ignore i/ o transactions on the primary interface 1: enable response to memory tr ansactions on the primary interface reset to 0 1 memory space enable rw 0: ignore memory read transactions on the primary interface 1: enable memory read tran sactions on the primary interface reset to 0 2 bus master enable rw 0: do not initiate memo ry or i/o transactions on the primary interface and disable response to memory and i/o tr ansactions on the secondary interface 1: enable the bridge to operate as a master on the primary interfaces for memory and i/o transactions forwarded from the secondary interface. if the primary of the reverse bridge is mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. reset to 0 3 special cycle enable ro 0: pi7c9x110 does not re spond as a target to special cycle transactions, so this bit is defined as read-only and must return 0 when read reset to 0 4 memory write and invalidate enable ro 0: pi7c9x110 does not originate a memory write and invalidate transaction. implements this bit as read-only and returns 0 when read (unless forwarding a transaction for another master). reset to 0 5 vga palette snoop enable ro / rw this bit applies to reverse bridge only. 0: ignore vga palette access on the primary 1: enable positive decoding response to vga palette writes on the primary interface with i/o address bits ad [9 :0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa alias; ad [15:0] ar e not decoded and may be any value) reset to 0 6 parity error response enable rw 0: may ignore any parity error that is detected and take its normal action 1: this bit if set, enables the setting of master data par ity error bit in the status register when poisoned tlp received or parity error is detected and takes its normal action reset to 0 7 wait cycle control ro wait cycle control not supported reset to 0 8 serr_l enable bit rw 0: disable 1: enable pi7c9x110 in forward bri dge mode to report non-fatal or fatal error message to the root complex. also , in reverse bridge mode to assert serr_l on the primary interface
pi7c9x110 pcie-to-pci reversible bridge page 34 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description reset to 0 9 fast back-to-back enable ro fast back-to-back enable not supported reset to 0 10 interrupt disable ro / rw this bit applies to reverse bridge only. 0: inta_l, intb_l, intc_l, and intd_l can be asserted on pci interface 1: prevent inta_l, intb_l, intc_l, and intd_l from being asserted on pci interface reset to 0 15:11 reserved ro reset to 00000 7.4.4 primary status register ? offset 04h bit function type description 18:16 reserved ro reset to 000 19 reserved (transparent mode ) ro reset to 0 20 capability list capable ro 1: pi7c9x110 supports the capability list (offset 34h in the pointer to the data structure) reset to 1 21 66mhz capable ro this bit applies to reverse bridge only. 1: 66mhz capable reset to 0 when forward bridge or 1 when reverse bridge. 22 reserved ro reset to 0 23 fast back-to-back capable ro this bit applies to reverse bridge only. 1: enable fast back-to-back transactions reset to 0 when forward bridge or 1 when reverse bridge in pci mode. 24 master data parity error detected rwc bit set if its parity erro r enable bit is set and eith er of the conditions occurs on the primary: forward bridge ? receives a completion marked poisoned poisons a write request reverse bridge ? detected parity error when receivi ng data or split response for read observes p_perr_l asserted when se nding data or receiving split response for write receives a split completion message indicating data parity error occurred for non-posted write reset to 0 26:25 devsel_l timing (medium decode) ro these bits apply to reverse bridge only. 00: fast devsel_l decoding 01: medium devsel_l decoding 10: slow devsel_l decoding 11: reserved reset to 00 when forward bridge or 01 when reverse bridge. 27 signaled target abort rwc forward bridge ? this bit is set when pi7c9x110 completes a request using completer abort status on the primary reverse bridge ? this bit is set to indicate a target abort on the primary reset to 0 28 received target abort rwc forward bridge ? this bit is set when pi7c9x110 receives a completion with completer abort completion status on the primary
pi7c9x110 pcie-to-pci reversible bridge page 35 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description reverse bridge ? this bit is set when pi7c9x110 detects a target abort on the primary reset to 0 29 received master abort rwc forward bridge ? this bit is set when pi7c9x110 r eceives a completion with unsupported request completion status on the primary reverse bridge ? this bit is set when pi7c9x110 detects a master abort on the primary 30 signaled system error rwc forward bridge ? this bit is set when pi7c9x110 sends an err_fatal or err_non_fatal message on the primary reverse bridge ? this bit is set when pi7c9x110 asserts serr_l on the primary reset to 0 31 detected parity error rwc forward bridge ? this bit is set when poisoned tlp is detected on the primary reverse bridge ? this bit is set when address or data parity error is detected on the primary reset to 0 7.4.5 revision id register ? offset 08h bit function type description 7:0 revision ro reset to 00000004h 7.4.6 class code register ? offset 08h bit function type description 15:8 programming interface ro subtractive d ecoding of pci-pci br idge not supported reset to 00000000 23:16 sub-class code ro sub-class code 00000100: pci-to-pci bridge reset to 00000100 31:24 base class code ro base class code 00000110: bridge device (transparent mode ) reset to 00000110 (transparent mode ) 7.4.7 cache line size register ? offset 0ch bit function type description 1:0 reserved ro bit [1:0] not supported reset to 00 2 cache line size rw 1: cache line size = 4 double words reset to 0 3 cache line size rw 1: cache line size = 8 double words reset to 0 4 cache line size rw 1: cache line size = 16 double words reset to 0 5 cache line size rw 1: cache line size = 32 double words
pi7c9x110 pcie-to-pci reversible bridge page 36 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description reset to 0 7:6 reserved ro bit [7:6] not supported reset to 00 7.4.8 primary latency timer register ? offset 0ch bit function type description 15:8 primary latency timer ro / rw 8 bits of primary latency timer in pci forward bridge ? ro with reset to 00h reverse bridge ? rw with reset to 00h in pci mode 7.4.9 primary header type register ? offset 0ch bit function type description 22:16 pci-to-pci bridge configuration (transparent mode) other bridge configuration (non-transparent mode ) ro ro pci-to-pci bridge configuration (10 ? 3fh) reset to 0000001 (transparent mode ) type-0 header format configuration (10-3fh) reset to 0000000 (non-transparent mode ) 23 single function device ro 0: indicates single function device reset to 0 31:24 reserved ro reset to 00h 7.4.10 reserved registers ? offset 10h to 17h 7.4.11 primary bus number register ? offset 18h bit function type description 7:0 primary bus number rw reset to 00h 7.4.12 secondary bus number register ? offset 18h bit function type description 15:8 secondary bus number rw reset to 00h 7.4.13 subordinate bus number register ? offset 18h bit function type description 23:16 subordinate bus number rw reset to 00h 7.4.14 secondary latency time register ? offset 18h bit function type description 31:24 secondary latency timer rw / ro secondary latency timer in pci forward bridge ? rw with reset to 00h in pci mode reverse bridge ? ro with reset to 00h 7.4.15 i/o base register ? offset 1ch
pi7c9x110 pcie-to-pci reversible bridge page 37 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 1:0 32-bit i/o addressing support ro 01: indicates pi7c9x110 supports 32-bit i/o addressing reset to 01 3:2 reserved ro reset to 00 7:4 i/o base rw indicates the i/o base (0000_0000h) reset to 0000 7.4.16 i/o limit register ? offset 1ch bit function type description 9:8 32-bit i/o addressing support ro 01: indicates pi7c9x110 supports 32-bit i/o addressing reset to 01 11:10 reserved ro reset to 00 15:12 i/o base rw indicates the i/o limit (0000_0fffh) reset to 0000 7.4.17 secondary status register ? offset 1ch bit function type description 20:16 reserved ro reset to 00000 21 66mhz capable ro indicates pi7c9x110 is 66mhz capable reset to 1 22 reserved ro reset to 0 23 fast back-to-back capable ro forward bridge: reset to 1 when secondary bus is in pci mode (supports fast back-to-back transactions) reverse bridge: reset to 0 (does not support fast back-to-back transactions) 24 master data parity error detected rwc this bit is set if its pa rity error enable bit is set and either of the conditions occur on the primary: forward bridge ? ? detected parity error when receivi ng data or split response for read ? observes s_perr_l asserted when sending data or receiving split response for write ? receives a split completion message indicating data parity error occurred for non-posted write reverse bridge ? ? receives a completion marked poisoned ? poisons a write request reset to 0 26:25 devsel_l timing (medium decoding) ro these bits apply to forward bridge only. 01: medium devsel_l decoding reset to 01 when forward mode or 00 when reverse mode. 27 signaled target abort rwc forward bridge ? bit is set when pi7c9x110 signals target abort reverse bridge ? bit is set when pi7c9x110 completes a request using completer abort completion status reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 38 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 28 received target abort rwc forward bridge ? bit is set when pi7c9x110 detects ta rget abort on the secondary interface reverse bridge ? bit is set when pi7c9x110 receives a completion with completer abort completion status on the secondary interface reset to 0 29 received master abort rwc forward bridge ? bit is set when pi7c9x110 detects master abort on the secondary interface reverse bridge ? bit is set when pi7c9x110 receives a completion with unsupported request completion status on the primary interface reset to 0 30 received system error rwc forward bridge ? bit is set when pi7c9x110 detects serr_l assertion on the secondary interface reverse bridge ? bit is set when pi7c9x110 receives an err_fatal or err_non_fatal message on the secondary interface reset to 0 31 detected parity error rwc forward bridge ? bit is set when pi7c9x110 detects address or data parity error reverse bridge ? bit is set when pi7c9x110 detects poisoned tlp on secondary interface reset to 0 7.4.18 memory base register ? offset 20h bit function type description 3:0 reserved ro reset to 0000 15:4 memory base rw memory base (80000000h) reset to 800h 7.4.19 memory limit register ? offset 20h bit function type description 19:16 reserved ro reset to 0000 31:20 memory limit rw memory limit (000fffffh) reset to 000h 7.4.20 prefetchable memory base register ? offset 24h bit function type description 3:0 64-bit addressing support ro 0001: indi cates pi7c9x110 supports 64-bit addressing reset to 0001 15:4 prefetchable memory base rw prefetchable memory base (00000000_80000000h) reset to 800h 7.4.21 prefetchable memory limit register ? offset 24h bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 39 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 19:16 64-bit addressing support ro 0001: indi cates pi7c9x110 supports 64-bit addressing reset to 0001 31:20 prefetchable memory limit rw pr efetchable memory limit (00000000_000fffffh) reset to 000h
pi7c9x110 pcie-to-pci reversible bridge page 40 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.22 prefetchable base upper 32-bit register ? offset 28h bit function type description 31:0 prefetchable base upper 32- bit rw bit [63:32] of prefetchable base reset to 00000000h 7.4.23 prefetchable limit upper 32-bit register ? offset 2ch bit function type description 31:0 prefetchable limit upper 32-bit rw bit [63:32] of prefetchable limit reset to 00000000h 7.4.24 i/o base upper 16-bit register ? offset 30h bit function type description 15:0 i/o base upper 16-bit rw bit [31:16] of i/o base reset to 0000h 7.4.25 i/o limit upper 16-bit register ? offset 30h bit function type description 31:16 i/o limit upper 16-bit rw bit [31:16] of i/o limit reset to 0000h 7.4.26 capability pointer ? offset 34h bit function type description 31:8 reserved ro reset to 0 7:0 capability pointer ro capability pointer to 80h reset to 80h 7.4.27 expansion rom base address register ? offset 38h bit function type description 31:0 expansion rom base address ro expansion rom not supported. reset to 00000000h 7.4.28 interrupt line register ? offset 3ch bit function type description 7:0 interrupt line rw these bits apply to reverse bridge only. for initialization code to program to tell which input of the interrupt controller the pi7c9x110?s inta_l in connected to. reset to 00000000
pi7c9x110 pcie-to-pci reversible bridge page 41 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.29 interrupt pin register ? offset 3ch bit function type description 15:8 interrupt pin ro these bits apply to reverse bridge only. designates interrupt pin inta_l, is used reset to 00h when forward mode or 01h when reverse mode. 7.4.30 bridge control register ? offset 3ch bit function type description 16 parity error response enable rw 0: ignore parity errors on the secondary 1: enable parity erro r detection on secondary forward bridge ? controls the response to uncorrectable a ddress attribute and data errors on the secondary reverse bridge ? controls the setting of the master data parity error bit in response to a received poisoned tlp from the secondary (pcie link) reset to 0 17 serr_l enable rw 0: disable the forwarding of serr_l to err_fatal and err_nonfatal 1: enable the forwarding of serr_l to err_fatal and err_nonfatal reset to 0 (forward bridge) ro bit for reverse bridge 18 isa enable rw 0: forward downstream all i/o addresses in the address range defined by the i/o base and limit registers 1: forward upstream all i/o addresses in the address range defined by the i/o base and limit registers that are in the first 64kb of pci i/o address space (top 768 bytes of each 1kb block) reset to 0 19 vga enable rw 0: do not forward vga compatible memory and i/o addresses from the primary to secondary, unless they are enabled for forwarding by the defined i/o and memory address ranges 1: forward vga compatible memory and i/o addresses from the primary and secondary (if the i/o enable and memory enable bits are set), independent of the isa enable bit 20 vga 16-bit decode rw 0: execute 10- bit address decodes on vga i/o accesses 1: execute 16-bit address decode on vga i/o accesses reset to 0 21 master abort mode rw 0: do not report mast er aborts (return ffffffffh on reads and discards data on write) 1: report master abort by signaling target abort if possible or by the assertion of serr_l (if enabled). reset to 0 22 secondary interface reset rw 0: do not force the assertion of reset_l on secondary pci bus for forward bridge, or do not generate a hot rese t on the pcie link for reverse bridge 1: force the assertion of reset_l on secondary pci bus for forward bridge, or generate a hot reset on the pcie link for reverse bridge reset to 0 23 fast back-to-back enable ro fast back-to-back not supported reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 42 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 24 primary master timeout rw 0: primary discard timer counts 2 15 pci clock cycles 1: primary discard timer counts 2 10 pci clock cycles forward bridge ? bit is ro and ignored by the pi7c9x110 reset to 0 25 secondary master timeout rw 0: secondary discard timer counts 2 15 pci clock cycles 1: secondary discard timer counts 2 10 pci clock cycles reverse bridge ? bit is ro and ignored by pi7c9x110 reset to 0 26 master timeout status rwc bit is set when the discard timer expires and a delayed completion is discarded at the pci interface for the forward or reverse bridge reset to 0 27 discard timer serr_l enable rw bit is set to enable to gene rate err_nonfatal or err_fatal for forward bridge, or assert p_serr_l for reverse bridge as a result of the expiration of the discard timer on the pci interface. reset to 0 31:28 reserved ro reset to 0000 7.4.31 pci data buffering co ntrol register ? offset 40h bit function type description 0 secondary internal arbiter?s park function rw 0: park to the last master 1: park to pi7c9x110 secondary port reset to 0 1 memory read prefetching dynamic control disable rw 0: enable memory read prefetchi ng dynamic control for pci to pcie read 1: disable memory read prefetching dynamic control for pci to pcie read reset to 0 2 completion data prediction control rw 0: enable completion data pr ediction for pci to pcie read. 1: disable completion data prediction reset to 0 3 reserved ro reset to 0 5:4 pci read multiple prefetch mode rw 00: one cache line prefetch if memo ry read multiple address is in prefetchable range at the pci interface 01: full prefetch if address is in pref etchable range at pci interface, and the pi7c9x110 will keep remaining data afte r it disconnects the external master during burst read with read multiple command until the discard timer expires 10: full prefetch if address is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data afte r the read multiple is terminated either by an external master or by the pi7c9x110, until the discard time expires reset to 10
pi7c9x110 pcie-to-pci reversible bridge page 43 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 7:6 pci read line prefetch mode rw 00: once cache line prefetch if memory read address is in prefetchable range at pci interface 01: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data afte r it is disconnected by an external master during burst read with read lin e command, until discard timer expires 10: full prefetch if memory read line a ddress is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data after the read line is te rminated either by an external master or by the pi7c9x110, until the discard timer expires reset to 00 9:8 pci read prefetch mode rw 00: one cache line prefet ch if memory read address is in prefetchable range at pci interface 01: reserved 10: full prefetch if memory read addr ess is in prefetchable range at pci interface 11: disconnect on the first dword reset to 00 10 pci special delayed read mode enable rw 0: retry any master at pci bus that repeats its transaction with command code changes. 1: allows any master at pci bus to change memory command code (mr, mrl, mrm) after it has received a retr y. the pi7c9x110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. reset to 0 11 reserved ro reset to 0 14:12 maximum memory read byte count rw maximum byte count is used by the pi7c9x110 when generating memory read requests on the pcie link in response to a memory read initiated on the pci bus and bit [9:8], bit [7:6], and bit [5:4] are set to ?full prefetch?. 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes reset to 000 7.4.32 chip control 0 register ? offset 40h bit function type description 15 flow control update control rw 0: flow control is updated for every two credits available 1: flow control is updated for every on credit available reset to 0 16 pci retry counter status rwc 0: the pci retr y counter has not expired since the last reset 1: the pci retry counter has expired since the last reset reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 44 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 18:17 pci retry counter control rw 00: no expiration limit 01: allow 256 retries before expiration 10: allow 64k retries before expiration 11: allow 2g retrie s before expiration reset to 00 19 pci discard timer disable rw 0: enable the pci di scard timer in conjunction with bit [27] offset 3ch (bridge control register) 1: disable the pci discard timer in conjunction with bit [27] offset 3ch (bridge control register) reset to 0 20 pci discard timer short duration rw 0: use bit [24] offset 3ch for forward bridge or bit [25] offset 3ch for reverse bridge to indicate how many pci clocks should be allowed before the pci discard timer expires 1: 64 pci clocks allowed before the pci discard timer expires reset to 0 22:21 configuration request retry timer counter value control rw 00: timer expires at 25us 01: timer expires at 0.5ms 10: timer expires at 5ms 11: timer expires at 25ms reset to 01 23 delayed transaction order control rw 0: enable out-of-order capability between delayed transactions 1: disable out-of-order capability between delayed transactions reset to 0 25:24 completion timer counter value control rw 00: timer expires at 50us 01: timer expires at 10ms 10: timer expires at 50ms 11: timer disabled reset to 01 26 isochronous traffic support enable rw 0: all memory transactions from pci to pcie will be mapped to tc0 1: all memory transactions from pci to pcie will be mapped to traffic class defined in bit [29:27] of offset 40h. reset to 0 29:27 traffic class used for isochronous traffic rw reset to 001 30 serial link interface loopback enable rw / ro 0: normal mode 1: enable serial link interface loopb ack mode (tx to rx) if tm0=low, tm1=high, tm2=high, msk_in=high, revrsb=high. pci transaction from pci bus will loop back to pci bus ro for forward bridge reset to 0 31 primary configuration access lockout ro / rw 0: pi7c9x110 configuration space can be accessed from both interfaces 1: pi7c9x110 configuration space can only be accessed from the secondary interface. primary bus accessed receives completion with crs status for forward bridge, or target retry for reverse bridge reset to 0 if tm0 is low
pi7c9x110 pcie-to-pci reversible bridge page 45 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.33 reserved register ? offset 44h bit function type description 31:0 reserved ro reset to 00000000h 7.4.34 arbiter enable register ? offset 48h bit function type description 0 enable arbiter 0 rw 0: disable arb itration for internal pi7c9x110 request 1: enable arbitration for internal pi7c9x110 request reset to 1 1 enable arbiter 1 rw 0: disable arbitration for master 1 1: enable arbitration for master 1 reset to 1 2 enable arbiter 2 rw 0: disable arbitration for master 2 1: enable arbitration for master 2 reset to 1 3 enable arbiter 3 rw 0: disable arbitration for master 3 1: enable arbitration for master 3 reset to 1 4 enable arbiter 4 rw 0: disable arbitration for master 4 1: enable arbitration for master 4 reset to 1 5 enable arbiter 5 rw 0: disable arbitration for master 5 1: enable arbitration for master 5 reset to 1 6 enable arbiter 6 rw 0: disable arbitration for master 6 1: enable arbitration for master 6 reset to 1 7 enable arbiter 7 rw 0: disable arbitration for master 7 1: enable arbitration for master 7 reset to 1 8 enable arbiter 8 rw 0: disable arbitration for master 8 1: enable arbitration for master 8 reset to 1 7.4.35 arbiter mode register ? offset 48h bit function type description 9 external arbiter bit ro 0: enable in ternal arbiter (if cfn_l is tied low) 1: use external arbiter (if cfn_l is tied high) reset to 0/1 according to what cfn_l is tied to 10 broken master timeout enable rw 0: broken master timeout disable 1: this bit enables the internal arb iter to count 16 pci bus cycles while waiting for frame_l to become activ e when a device?s pci bus gnt is active and the pci bus is idle. if the broken master timeout expires, the pci bus gnt for the device is de-asserted. reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 46 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 11 broken master refresh enable rw 0: a broken master will be ignored forever after de-asserting its req_l for at least 1 clock 1: refresh broken master state after a ll the other masters have been served once reset to 0 19:12 arbiter fairness counter rw 08h: these bits are the initialization value of a count er used by the internal arbiter. it controls the number of pc i bus cycles that the arbiter holds a device?s pci bus gnt active after detecting a pci bus req_l from another device. the counter is reloaded whenever a new pci bus gnt is asserted. for every new pci bus gnt, the counter is armed to decrement when it detects the new fall of frame_l. if the arbiter fairness counter is set to 00h, the arbiter will not remove a device?s pci bus gnt until the device has de- asserted its pci bus req. reset to 08h 20 gnt_l output toggling enable rw 0: gnt_l not de-asserted afte r granted master assert frame_l 1: gnt_l de-asserts for 1 clock after 2 cl ocks of the granted master asserting frame_l reset to 0 21 reserved ro reset to 0 7.4.36 arbiter priority register ? offset 48h bit function type description 22 arbiter priority 0 rw 0: low prio rity request to internal pi7c9x110 1: high priority request to internal pi7c9x110 reset to 1 23 arbiter priority 1 rw 0: low priority request to master 1 1: high priority request to master 1 reset to 0 24 arbiter priority 2 rw 0: low priority request to master 2 1: high priority request to master 2 reset to 0 25 arbiter priority 3 rw 0: low priority request to master 3 1: high priority request to master 3 reset to 0 26 arbiter priority 4 rw 0: low priority request to master 4 1: high priority request to master 4 reset to 0 27 arbiter priority 5 rw 0: low priority request to master 5 1: high priority request to master 5 reset to 0 28 arbiter priority 6 rw 0: low priority request to master 6 1: high priority request to master 6 reset to 0 29 arbiter priority 7 rw 0: low priority request to master 7 1: high priority request to master 7 reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 47 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 30 arbiter priority 8 rw 0: low priority request to master 8 1: high priority request to master 8 reset to 0 31 reserved ro reset to 0 7.4.37 reserved registers ? offset 4ch ? 64h 7.4.38 express transmitter/receiver register ? offset 68h bit function type description 1:0 nominal driver current control rw 00: 20ma 01: 10ma 10: 28ma 11: reserved reset to 00 5:2 driver current scale multiple control rw 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current reset to 0000 11:8 driver de-emphasis level control rw 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db reset to 1000 13:12 transmitter termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00
pi7c9x110 pcie-to-pci reversible bridge page 48 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 15:14 receiver termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00 29:16 reserved ro reset to 00h 7.4.39 upstream memory write fragment control register ? offset 68h bit function type description 31:30 memory write fragment control rw upstream memory write fragment control 00: fragment at 32-byte boundary 01: fragment at 64-byte boundary 1x: fragement at 128-byte boundary reset to 10h 7.4.40 reserved register ? offset 6ch 7.4.41 eeprom autoload control/status register ? offset 70h bit function type description 0 initiate eeprom read or write cycle rw this bit will be reset to 0 afte r the eeprom operation is finished. 0: eeprom autoload disabled 0 -> 1: starts the eeprom read or write cycle reset to 0 1 control command for eeprom rw 0: read 1: write reset to 0 2 eeprom error ro 0: eeprom acknowledge is always received during the eeprom cycle 1: eeprom acknowledge is not received during eeprom cycle reset to 0 3 eprom autoload complete status ro 0: eeprom autoload is not successfully completed 1: eeprom autoload is successfully completed reset to 0 5:4 eeprom clock frequency control rw where pclk is 125mhz 00: pclk / 4096 01: pclk / 2048 10: pclk / 1024 11: pclk / 128 reset to 00 6 eeprom autoload control rw 0: enable eeprom autoload 1: disable eeprom autoload reset to 0 7 fast eeprom autoload control rw 0: normal speed of eeprom autoload 1: increase eeprom autoload by 32x reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 49 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 8 eeprom autoload status ro 0: eeprom autoload is not on going 1: eeprom autoload is on going reset to 0 15:9 eeprom word address rw eeprom word address for eeprom cycle reset to 0000000 31:16 eeprom data rw eeprom data to be written into the eeprom reset to 0000h
pi7c9x110 pcie-to-pci reversible bridge page 50 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.42 reserved register ? offset 74h 7.4.43 gpio data and control register ? offset 78h bit function type description 11:0 reserved ro reset to 000h 15:12 gpio output write-1-to- clear rw reset to 0h 19:16 gpio output write-1-to-set rw reset to 0h 23:20 gpio output enable write- 1-to-clear rw reset to 0h 27:24 gpio output enable write- 1-to-set rw reset to 0h 31:28 gpio input data register ro reset to 0h 7.4.44 reserved register ? offset 7ch 7.4.45 capability id register ? offset 80h bit function type description 7:0 capability id ro capability id reset to 07h 7.4.46 next capability pointer register ? offset 80h bit function type description 15:8 next capability pointer ro point to power management reset to 90h 7.4.47 secondary status register ? offset 80h bit function type description 16 64-bit device on secondary bus interface ro 64-bit not supported reset to 0 17 133mhz capable ro when this bit is 1, pi7c9x110 is 133mhz capable on its secondary bus interface reset to 1 in forward bridge mode or 0 in reverse bridge mode 18 split completion discarded ro / rwc this bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode when this is set to 1, a split completion has been discarded by pi7c9x110 at secondary bus because the requester did not accept the split completion transaction reset to 0 19 unexpected split completion rwc this bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode when this is set to 1, an unexpected split completion has been received with the requester id equaled to the secondary bus number, device number, and function number at the pi7x9x110 secondary bus interface reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 51 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 20 split completion overrun rwc when this bit is set to 1, a split completion has been terminated by pi7c9x110 with either a retry or disc onnect at the next adb due to the buffer full condition reset to 0 21 split request delayed rwc when this bit is set to 1, a split request is delayed because pi7c9x110 is not able to forward the split request tran saction to its secondary bus due to insufficient room with in the limit specified in the split transaction commitment limit field of the downstream split transaction control register reset to 0 24:22 secondary clock fre quency ro these bits are only meaningful in forward bridge mode. in reverse bridge mode, all three bits are set to zero. 000: conventional pci mode (minim um clock period not applicable) 001: 66mhz (minimum clock period is 15ns) 010: 100 to 133mhz (minimum clock period is 7.5ns) 011: reserved 1xx: reserved reset to 000 31:25 reserved ro 0000000 7.4.48 bridge status register ? offset 84h bit function type description 2:0 function number ro function number (ad [10: 8] of a type 0 configuration transaction) reset to 000 7:3 device number ro device number (ad [15:11] of a type 0 configuration transaction) is assigned to the pi7c9x110 by the connection of system hardware. each time the pi7c9x110 is addressed by a configura tion write transaction, the bridge updates this register with the contents of ad [15:11] of the address phase of the configuration transaction, regardle ss of which register in the pi7c9x110 is addressed by the transaction. the pi7c9x110 is addressed by a configuration write tran saction if all of the following are true: ? the transaction uses a configuration write command ? idsel is asserted during the address phase ? ad [1:0] are 00 (type o configuration transaction) ? ad [10:8] of the configuration addr ess contain the appropriate function number reset to 11111 15:8 bus number ro additional address from wh ich the contents of the primary bus number register on type 1 configuration space header is read. the pi7c9x110 uses the bus number, device number, and function number fields to create a completer id when responding with a split completion to a read of an internal pi7c9x110 register. these fields are al so used for cases when one interface is in conventional pci mode. reset to 11111111 16 64-bit device on primary bus interface ro 64-bit not supported reset to 0 17 133mhz capable ro when this bit is 1, pi7c9x110 is 133mhz capable on its primary bus interface reset to 0 in forward bridge mode or 1 in reverse bridge mode
pi7c9x110 pcie-to-pci reversible bridge page 52 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 18 split completion discarded ro / rwc this bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode when this is set to 1, a split completion has been discarded by pi7c9x110 at primary bus because the requester did not accept the split completion transaction reset to 0 19 unexpected split completion rwc this bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode when this is set to 1, an unexpected split completion has been received with the requester id equaled to the primary bus number, device number, and function number at the pi7x9x110 primary bus interface reset to 0 20 split completion overrun rwc when this bit is set to 1, a split completion has been terminated by pi7c9x110 with either a retry or disc onnect at the next adb due to the buffer full condition reset to 0 21 split request delayed rwc when this bit is set to 1, a split request is delayed because pi7c9x110 is not able to forward the split request tran saction to its primary bus due to insufficient room with in the limit specified in the split transaction commitment limit field of the downstream split transaction control register reset to 0 31:22 reserved ro 0000000000 7.4.49 upstream split transaction register ? offset 88h bit function type description 15:0 upstream split transaction capability ro upstream split transaction capability sp ecifies the size of the buffer (in the unit of adqs) to store split completions fo r memory read. it applies to the requesters on the secondary bus in addressing the completers on the primary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h 31:16 upstream split transaction commitment limit rw upstream split transaction commitment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x110 is allowed to forward all split requests of any size rega rdless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 7.4.50 downstream split transaction register ? offset 8ch bit function type description 15:0 downstream split transaction capability ro downstream split transaction capability specifies the size of the buffer (in the unit of adqs) to store split completions for memory read. it applies to the requesters on the primary bus in addressing the completers on the secondary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h
pi7c9x110 pcie-to-pci reversible bridge page 53 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31:16 downstream split transaction commitment limit rw downstream split transaction comm itment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x110 is allowed to forward all split requests of any size rega rdless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 7.4.51 power management id register ? offset 90h bit function type description 7:0 power management id ro po wer management id register reset to 01h 7.4.52 next capability pointer register ? offset 90h bit function type description 15:8 next pointer ro next pointer (point to subsystem id and subsystem vendor id) reset to a8h 7.4.53 power management capability register ? offset 90h bit function type description 18:16 version number ro version number that complies with revision 2.0 of the pci power management interface specification. reset to 010 19 pme clock ro pme clock is not required for pme_l generation reset to 0 20 reserved ro reset to 0 21 device specific initialization (dsi) ro dsi ? no special initialization of th is function beyond the standard pci configuration header is required following transition to the d0 un-initialized state reset to 0 24:22 aux current ro 000: 0ma 001: 55ma 010: 100ma 011: 160ma 100: 220ma 101: 270ma 110: 320ma 111: 375ma reset to 001 25 d1 power management ro d1 pow er management is not supported reset to 0 26 d2 power management ro d2 pow er management is not supported reset to 0 31:27 pme_l support ro pme_l is supported in d3 cold, d3 hot, and d0 states. reset to 11001
pi7c9x110 pcie-to-pci reversible bridge page 54 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.54 power management control and status register ? offset 94h bit function type description 1:0 power state rw power state is used to determ ine the current power state of pi7c9x110. if a non-implemented state is written to th is register, pi7c9x110 will ignore the write data. when present state is d3 and changing to d0 state by programming this register, the power state change causes a device reset without activating the rese t_l of pci bus interface 00: d0 state 01: d1 state not implemented 10: d2 state not implemented 11: d3 state reset to 00 7:2 reserved ro reset to 000000 8 pme enable rws 0: pme_l assertion is disabled 1: pme_l assertion is enabled reset to 0 12:9 data select ro data re gister is not implemented reset to 0000 14:13 data scale ro data re gister is not implemented reset to 00 15 pme status rwcs pme_l is supported reset to 0 7.4.55 pci-to-pci support exten sion register ? offset 94h bit function type description 21:16 reserved ro reset to 000000 22 b2/b3 support ro 0: b2 / b3 not support for d3hot reset to 0 23 pci bus power/clock control enable ro 0: pci bus power/clock disabled reset to 0 31:24 data register ro data register is not implemented reset to 00h 7.4.56 reserved registers ? offset 98h ? 9ch 7.4.57 capability id register ? offset a0h bit function type description 7:0 capability id ro capability id fo r slot identification. si is o ff by default but can be turned on through eeprom interface reset to 04h 7.4.58 next pointer register ? offset a0h bit function type description 15:8 next pointer ro next pointer ? poi nts to pci express capabilities register reset to b0h
pi7c9x110 pcie-to-pci reversible bridge page 55 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.59 slot number register ? offset a0h bit function type description 20:16 expansion slot number rw expansion slot number reset to 00000 21 first in chassis rw first in chassis reset to 0 23:22 reserved ro reset to 00 7.4.60 chassis number register ? offset a0h bit function type description 31:24 chassis number rw chassis number reset to 00h 7.4.61 secondary clock and clkrun control register ? offset a4h bit function type description 1:0 s_clkout0 enable rw s_clkout (slot 0) enable for forward bridge mode only 00: enable s_clkout0 01: enable s_clkout0 10: enable s_clkout0 11: disable s_clkout0 and driven low reset to 00 3:2 s_clkout1 enable rw s_clkout (slot 1) enable for forward bridge mode only 00: enable s_clkout1 01: enable s_clkout1 10: enable s_clkout1 11: disable s_clkout1 and driven low reset to 00 5:4 s_clkout2 enable rw s_clkout (slot 2) enable for forward bridge mode only 00: enable s_clkout2 01: enable s_clkout2 10: enable s_clkout2 11: disable s_clkout2 and driven low reset to 00 7:6 s_clkout3 enable rw s_clkout (slot 3) enable for forward bridge mode only 00: enable s_clkout3 01: enable s_clkout3 10: enable s_clkout3 11: disable s_clkout3 and driven low reset to 00 8 s_clkout4 enable rw s_clkout (device 1) enable for forward bridge mode only 0: enable s_clkout4 1: disable s_clkout4 and driven low reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 56 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 9 s_clkout5 enable rw s_clkout (device 2) enable for forward bridge mode only 0: enable s_clkout5 1: disable s_clkout5 and driven low reset to 0 10 s_clkout6 enable rw s_clkout (device 3) enable for forward bridge mode only 0: enable s_clkout6 1: disable s_clkout6 and driven low reset to 0 11 s_clkout7 enable rw s_clkout (device 4) enable for forward bridge mode only 0: enable s_clkout7 1: disable s_clkout7 and driven low reset to 0 12 s_clkout8 enable rw s_clkout (the bridge ) enable for forward bridge mode only 0: enable s_clkout8 1: disable s_clkout8 and driven low reset to 0 13 secondary clock stop status ro secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped reset to 0 14 secondary clkrun protocol enable rw 0: disable protocol 1: enable protocol reset to 0 15 clkrun mode rw 0: stop the secondary cl ock only when bridge is at d3hot state 1: stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus reset to 0 31:16 reserved ro reset to 0000h 7.4.62 capability id register ? offset a8h bit function type description 7:0 capability id ro capability id for subsystem id and subsystem vendor id reset to 0dh 7.4.63 next pointer register ? offset a8h bit function type description 15:8 next item pointer ro next item pointer (point to pci express capability by default but can be programmed to a0h if slot identif ication capability is enabled) reset to b0h 7.4.64 reserved register ? offset a8h bit function type description 31:16 reserved ro reset to 0000h
pi7c9x110 pcie-to-pci reversible bridge page 57 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.65 subsystem vendor id register ? offset ach bit function type description 15:0 subsystem vendor id ro subsystem vendor id id entifies the particular add-in card or subsystem reset to 00h 7.4.66 subsystem id register ? offset ach bit function type description 31:16 subsystem id ro subsystem id identifie s the particular add-in card or subsystem reset to 00h 7.4.67 pci express capability id register ? offset b0h bit function type description 7:0 pci express capability id ro pci express capability id reset to 10h 7.4.68 next capability pointer register ? offset b0h bit function type description 15:8 next item pointer ro next ite m pointer (points to vpd register) reset to d8h 7.4.69 pci express capabilit y register ? offset b0h bit function type description 19:16 capability version ro reset to 1h 23:20 device / port type ro 0000: pci express endpoint device 0001: legacy pci express endpoint device 0100: root port of pci express root complex 0101: upstream port of pci express switch 0110: downstream port of pci express switch 0111: pci express to pci bridge 1000: pci to pci express bridge others: reserved reset to 7h for forward bridge or 8h for reverse bridge 24 slot implemented ro reset to 0 for fo rward bridge or 1 for reverse bridge 29:25 interrupt message nu mber ro reset to 0h 31:30 reserved ro reset to 0 7.4.70 device capability register ? offset b4h bit function type description 2:0 maximum payload size ro 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 001
pi7c9x110 pcie-to-pci reversible bridge page 58 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 4:3 phantom functions ro no phantom functions supported reset to 00 5 8-bit tag field ro 8-bit tag field supported reset to 1 8:6 endpoint l0?s latency ro endpoint l0?s acceptable latency 000: less than 64 ns 001: 64 ? 128 ns 010: 128 ? 256 ns 011: 256 ? 512 ns 100: 512 ns ? 1 us 101: 1 ? 2 us 110: 2 ? 4 us 111: more than 4 us reset to 000 11:9 endpoint l1?s latency ro endpoint l1?s acceptable latency 000: less than 1 us 001: 1 ? 2 us 010: 2 ? 4 us 011: 4 ? 8 us 100: 8 ? 16 us 101: 16 ? 32 us 110: 32 ? 64 us 111: more than 64 us reset to 000 12 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 13 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 17:15 reserved ro reset to 000 25:18 captured slot power limit value ro these bits are set by the set_slot_power_limit message reset to 00h 27:26 captured slot power limit scale ro this value is set by the set_slot_power_limit message reset to 00 31:28 reserved ro reset to 0h 7.4.71 device control register ? offset b8h bit function type description 0 correctable error reporting enable rw reset to 0h 1 non-fatal error reporting enable rw reset to 0h 2 fatal error reporting enable rw reset to 0h
pi7c9x110 pcie-to-pci reversible bridge page 59 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 3 unsupported request reporting enable rw reset to 0h 4 relaxed ordering enable ro relaxed ordering disabled reset to 0h 7:5 max payload size rw this field sets the maximum tlp payload size for the pi7c9x110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 000 8 extended tag field enable rw reset to 0 9 phantom functions enable ro phantom functions not supported reset to 0 10 auxiliary power pm enable ro auxiliary power pm not supported reset to 0 11 no snoop enable ro bridge never sets the no snoop attribute in the transaction it initiates reset to 0 14:12 maximum read request size rw this field sets the maximum read request size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 2h 15 configuration retry enable rw reset to 0 7.4.72 device status register ? offset b8h bit function type description 16 correctable error detected rwc reset to 0 17 non-fatal error detected rwc reset to 0 18 fatal error detected rwc reset to 0 19 unsupported request detected rwc reset to 0 20 aux power detected ro reset to 1 21 transaction pending ro 0: no transaction is pending on transaction layer interface 1: transaction is pending on transaction layer interface reset to 0 31:22 reserved ro reset to 0000000000 7.4.73 link capability register ? offset bch bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 60 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 3:0 maximum link speed ro indicates th e maximum speed of the express link 0001: 2.5gb/s link reset to 1 9:4 maximum link width ro indicates the maximu m width of the express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 11:10 aspm support ro this field indicates the level of active state power management support 00: reserved 01: l0?s entry supported 10: reserved 11: l0?s and l1?s supported reset to 11 14:12 l0?s exit latency ro reset to 3h 17:15 l1?s exit latency ro reset to 0h 23:18 reserved ro reset to 0h 31:24 port number ro reset to 00h 7.4.74 link control register ? offset c0h bit function type description 1:0 aspm control rw this field controls th e level of aspm supported on the express link 00: disabled 01: l0?s entry enabled 10: l1?s entry enabled 11: l0?s and l1?s entry enabled reset to 00 2 reserved ro reset to 0 3 read completion boundary (rcb) ro read completion boundary not supported reset to 0 4 link disable ro / rw ro for forward bridge reset to 0 5 retrain link ro / rw ro for forward bridge reset to 0 6 common clock configuration rw reset to 0 7 extended sync rw reset to 0 15:8 reserved ro reset to 00h 7.4.75 link status register ? offset c0h bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 61 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 19:16 link speed ro this field indicates the negotiated speed of the express link 001: 2.5gb/s link reset to 1h 25:20 negotiated link width ro 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 26 link train error ro reset to 0 27 link training ro reset to 0 28 slot clock configuration ro reset to 1 31:29 reserved ro reset to 0 7.4.76 slot capability register ? offset c4h bit function type description 0 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 1 power controller present ro reset to 0 2 mrl sensor present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 3 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 4 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 5 hot plug surprise ro reset to 0 6 hot plug capable ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14:7 slot power limit value ro reset to 00h 16:15 slot power limit scale ro reset to 00 18:17 reserved ro reset to 00 31:19 physical slot number ro reset to 0 7.4.77 slot control register ? offset c8h bit function type description 0 attention button present enable rw reset to 0 1 power fault detected enable rw reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 62 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 2 mrl sensor changed enable rw reset to 0 3 presence detect changed enable rw reset to 0 4 command completed interrupt enable rw reset to 0 5 hot plug interrupt enable rw reset to 0 7:6 attention indicator control rw reset to 0 9:8 power indicator control rw reset to 0 10 power controller control rw reset to 0 15:11 reserved ro reset to 0 7.4.78 slot status register ? offset c8h bit function type description 16 attention button pressed ro reset to 0 17 power fault detected ro reset to 0 18 mrl sensor changed ro reset to 0 19 presence detect changed ro reset to 0 20 command completed ro reset to 0 21 mrl sensor state ro reset to 0 22 presence detect state ro reset to 0 31:23 reserved ro reset to 0 7.4.79 xpip configuration register 0 ? offset cch bit function type description 0 hot reset enable rw reset to 0 1 loopback function enable rw reset to 0 2 cross link function enable rw reset to 0 3 software direct to configuration state when in ltssm state rw reset to 0 4 internal selection for debug mode rw reset to 0 7:5 negotiate lane number of times rw reset to 3h 12:8 ts1 number counter rw reset to 10h 15:13 reserved ro reset to 0 31:16 ltssm enter l1 timer default value rw reset to 0400h 7.4.80 xpip configuration register 1 ? offset d0h bit function type description 9:0 l0?s lifetime timer rw reset to 0 15:10 reserved ro reset to 0 31:16 l1 lifetime timer rw reset to 0 7.4.81 xpip configuration register 2 ? offset d4h bit function type description 7:0 cdr recovery time (in the number of fts order sets) rw reset to 54h a fast training sequence order set co mposes of one k28.5 (com) symbol and three k28.1 symbols. 14:8 l0?s exit to l0 latency rw reset to 2h 15 reserved ro reset to 0 22:16 l1 exit to l0 latency rw reset to 19h 23 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 63 of 144 pericom semiconductor ? confidential april 2010, revision 3.0
pi7c9x110 pcie-to-pci reversible bridge page 64 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.82 hot swap switch debounce counter ? offset d4h bit function type description 31:24 hot swap debounce counter ro / rw if hot swap is enabled, this counter is read-write able. this counter is read only (ro) if hot swap is disabled 00h: 1ms 01h: 2ms 02h: 3ms 03h: 4ms ? ffh: 256ms reset to 0 7.4.83 capability id register ? offset d8h bit function type description 7:0 capability id for vpd register ro reset to 03h 7.4.84 next pointer register ? offset d8h bit function type description 15:8 next pointer ro next pointer (f0h, points to msi capabilities) reset to f0h 7.4.85 vpd register ? offset d8h bit function type description 17:16 reserved ro reset to 0 23:18 vpd address for read/write cycle rw reset to 0 30:24 reserved ro reset to 0 31 vpd operation rw 0: generate a read cycle fr om the eeprom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?0? until eeprom cycle is finished, after which the bit is then set to ?1?. data for reads is available at register ech. 1: generate a write cycle to the eep rom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?1? until eeprom cycle is finished, after which it is then cleared to ?0?. reset to 0 7.4.86 vpd data register ? offset dch bit function type description 31:0 vpd data rw vpd data (eeprom data [address + 0x40]) the least significant byte of this regist er corresponds to the byte of vpd at the address specified by the vpd addre ss register. the data read form or written to this register uses the normal pci byte tr ansfer capabilities. reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 65 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.87 reserved registers ? offset e0h ? ech 7.4.88 message signaled interrupts id register ? f0h bit function type description 7:0 capability id for msi registers ro reset to 05h 7.4.89 next capabilities pointer register ? f0h bit function type description 15:8 next pointer ro next pointer (00h indicates the end of capabilities) reset to 00h 7.4.90 message control register ? offset f0h bit function type description 16 msi enable rw 0: disable msi and default to intx for interrupt 1: enable msi for interrupt service and ignore intx interrupt pins 19:17 multiple message capable ro 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 22:20 multiple message enable rw 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 23 64-bit address capable rw reset to 1 31:24 reserved ro reset to 00h 7.4.91 message address register ? offset f4h bit function type description 1:0 reserved ro reset to 00 31:2 system specified message address rw reset to 0 7.4.92 message upper address register ? offset f8h bit function type description 31:0 system specified message upper address rw reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 66 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.93 message data register ? offset fch bit function type description 15:0 system specified message data rw reset to 0 31:16 reserved ro reset to 0 7.4.94 advance error repo rting capability id re gister ? offset 100h bit function type description 15:0 advance error reporting capability id ro reset to 0001h 7.4.95 advance error report ing capability version register ? offset 100h bit function type description 19:16 advance error reporting capability version ro reset to 1h 7.4.96 next capability offs et register ? offset 100h bit function type description 31:20 next capability offset ro next cap ability offset (150h poi nts to vc capability) reset to 150h 7.4.97 uncorrectable error status register ? offset 104h bit function type description 0 training error status rwcs reset to 0 3:1 reserved ro reset to 0 4 data link protocol error status rwcs reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp status rwcs reset to 0 13 flow control protocol error status rwcs reset to 0 14 completion timeout status rwcs reset to 0 15 completer abort status rwcs reset to 0 16 unexpected completion status rwcs reset to 0 17 receiver overflow status rwcs reset to 0 18 malformed tlp status rwcs reset to 0 19 ecrc error status rwcs reset to 0 20 unsupported request error status rwcs reset to 0 31:21 reserved ro reset to 0 7.4.98 uncorrectable error mask register ? offset 108h bit function type description 0 training error mast rws reset to 0 3:1 reserved ro reset to 0 4 data link protocol error mask rws reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp mask rws reset to 0 13 flow control protocol error mask rws reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 67 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 14 completion timeout mask rws reset to 0 15 completion abort mask rws reset to 0 16 unexpected completion mask rws reset to 0 17 receiver overflow mask rws reset to 0 18 malformed tlp mask rws reset to 0 19 ecrc error mask rws reset to 0 20 unsupported request error mask rws reset to 0 31:21 reserved ro reset to 0 7.4.99 uncorrectable error severity register ? offset 10ch bit function type description 0 training error severity rws reset to 1 3:1 reserved ro reset to 0 4 data link protocol error severity rws reset to 1 11:5 reserved ro reset to 0 12 poisoned tlp severity rws reset to 0 13 flow control protocol error severity rws reset to 1 14 completion timeout severity rws reset to 0 15 completer abort seve rity rws reset to 0 16 unexpected completion severity rws reset to 0 17 receiver overflow severity rws reset to 1 18 malformed tlp severity rws reset to 1 19 ecrc error severity rws reset to 0 20 unsupported request error severity rws reset to 0 31:21 reserved ro reset to 0 7.4.100 correctable error stat us register ? offset 110h bit function type description 0 receiver error status rwcs reset to 0 5:1 reserved ro reset to 0 6 bad tlp status rwcs reset to 0 7 bad dllp status rwcs reset to 0 8 replay_num rollover status rwcs reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout status rwcs reset to 0 31:13 reserved ro reset to 0 7.4.101 correctable error ma sk register ? offset 114h bit function type description 0 receiver error mask rws reset to 0 5:1 reserved ro reset to 0 6 bad tlp mask rws reset to 0 7 bad dllp mask rws reset to 0 8 replay_num rollover mask rws reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout mask rws reset to 0 31:13 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 68 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.4.102 advanced error capabilities and control register ? offset 118h bit function type description 4:0 first error pointer ros reset to 0h 5 ecrc generation capable ro reset to 1 6 ecrc generation enable rws reset to 0 7 ecrc check capable ro reset to 1 8 ecrc check enable rws reset to 0 31:9 reserved ro reset to 0 7.4.103 header log register 1 ? offset 11ch bit function type description 7:0 header byte 3 ros reset to 0 15:8 header byte 2 ros reset to 0 23:16 header byte 1 ros reset to 0 31:24 header byte 0 ros reset to 0 7.4.104 header log register 2 ? offset 120h bit function type description 7:0 header byte 7 ros reset to 0 15:8 header byte 6 ros reset to 0 23:16 header byte 5 ros reset to 0 31:24 header byte 4 ros reset to 0 7.4.105 header log register 3 ? offset 124h bit function type description 7:0 header byte 11 ros reset to 0 15:8 header byte 10 ros reset to 0 23:16 header byte 9 ros reset to 0 31:24 header byte 8 ros reset to 0 7.4.106 header log register 4 ? offset 128h bit function type description 7:0 header byte 15 ros reset to 0 15:8 header byte 14 ros reset to 0 23:16 header byte 13 ros reset to 0 31:24 header byte 12 ros reset to 0 7.4.107 secondary uncorrectable error status register ? offset 12ch bit function type description 0 target abort on split completion status rwcs reset to 0 1 master abort on split completion status rwcs reset to 0 2 received target abort status rwcs reset to 0 3 received master abort status rwcs reset to 0 4 reserved ro reset to 0 5 unexpected split completion error status rwcs reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 69 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 6 uncorrectable split completion message data error status rwcs reset to 0 7 uncorrectable data error status rwcs reset to 0 8 uncorrectable attribute error status rwcs reset to 0 9 uncorrectable address error status rwcs reset to 0 10 delayed transaction discard timer expired status rwcs reset to 0 11 perr_l assertion detected status rwcs reset to 0 12 serr_l assertion detected status rwcs reset to 0 13 internal bridge error status rwcs reset to 0 31:14 reserved ro reset to 0 7.4.108 secondary uncorrectable e rror mask register ? offset 130h bit function type description 0 target abort on split completion mask rws reset to 0 1 master abort on split completion mask rws reset to 0 2 received target abort mask rws reset to 0 3 received master abort mask rws reset to 1 4 reserved ro reset to 0 5 unexpected split completion error mask rws reset to 1 6 uncorrectable split completion message data error mask rws reset to 0 7 uncorrectable data error mask rws reset to 1 8 uncorrectable attribute error mask rws reset to 1 9 uncorrectable address error mask rws reset to 1 10 delayed transaction discard timer expired mask rws reset to 1 11 perr_l assertion detected mask rws reset to 0 12 serr_l assertion detected mask rws reset to 1 13 internal bridge error mask rws reset to 0 31:14 reserved ro reset to 0 7.4.109 secondary uncorrectable erro r severity register ? offset 134h bit function type description 0 target abort on split completion severity rws reset to 0 1 master abort on split completion severity rws reset to 0 2 received target abort severity rws reset to 0 3 received master abort severity rws reset to 0 4 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 70 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 5 unexpected split completion error severity rws reset to 0 6 uncorrectable split completion message data error severity rws reset to 1 7 uncorrectable data error severity rws reset to 0 8 uncorrectable attribute error severity rws reset to 1 9 uncorrectable address error severity rws reset to 1 10 delayed transaction discard timer expired severity rws reset to 0 11 perr_l assertion detected severity rws reset to 0 12 serr_l assertion detected severity rws reset to 1 13 internal bridge error severity rws reset to 0 31:14 reserved ro reset to 0 7.4.110 secondary error capability and control register ? offset 138h bit function type description 4:0 secondary first error pointer row reset to 0 31:5 reserved ro reset to 0 7.4.111 secondary header log re gister ? offset 13ch ? 148h bit function type description 35:0 transaction attribute ros tran saction attribute, cbe [3:0] and ad [31:0] during attribute phase reset to 0 39:36 transaction command lower ros transaction command lower, cbe [3:0] during first address phase reset to 0 43:40 transaction command upper ros transaction command upper, cbe [3 :0] during second address phase of dac transaction reset to 0 63:44 reserved ros reset to 0 95:64 transaction address ros transaction addr ess, ad [31:0] during first address phase reset to 0 127:96 transaction address ros transaction addres s, ad [31:0] during second address phase of dac transaction reset to 0 7.4.112 reserved register ? offset 14ch 7.4.113 vc capability id register ? offset 150h bit function type description 15:0 vc capability id ro reset to 0002h 7.4.114 vc capability version register ? offset 150h
pi7c9x110 pcie-to-pci reversible bridge page 71 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 19:16 vc capability version ro reset to 1h 7.4.115 next capability o ffset register ? offset 150h bit function type description 31:20 next capability offset ro next capability offset ? th e end of capabilities reset to 0 7.4.116 port vc capability register 1 ? offset 154h bit function type description 2:0 extended vc count ro reset to 0 3 reserved ro reset to 0 6:4 low priority extended vc count ro reset to 0 7 reserved ro reset to 0 9:8 reference clock ro reset to 0 11:10 port arbitration table entry size ro reset to 0 31:12 reserved ro reset to 0 7.4.117 port vc capability register 2 ? offset 158h bit function type description 7:0 vc arbitration capability ro reset to 0 23:8 reserved ro reset to 0 31:24 vc arbitration table offset ro reset to 0 7.4.118 port vc control register ? offset 15ch bit function type description 0 load vc arbitration table ro reset to 0 3:1 vc arbitration select ro reset to 0 15:4 reserved ro reset to 0 7.4.119 port vc status register ? offset 15ch bit function type description 16 vc arbitration table status ro reset to 0 31:17 reserved ro reset to 0 7.4.120 vc0 resource capability register ? offset 160h bit function type description 7:0 port arbitration capability ro reset to 0 13:8 reserved ro reset to 0 14 advanced packet switching ro reset to 0 15 reject snoop transactions ro reset to0 22:16 maximum time slots ro reset to 0 23 reserved ro reset to 0 31:24 port arbitration table offset ro reset to 0 7.4.121 vc0 resource control register ? offset 164h bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 72 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 0 tc / vc map ro for tc0 reset to 1 7:1 tc / vc map rw for tc7 to tc1 reset to 7fh 15:8 reserved ro reset to 0 16 load port arbitration table ro reset to 0 19:17 port arbitration select ro reset to 0 23:20 reserved ro reset to 0 26:24 vc id ro reset to 0 30:27 reserved ro reset to 0 31 vc enable ro reset to 1 7.4.122 vc0 resource status register ? offset 168h bit function type description 0 port arbitration table 1 ro reset to 0 1 vc0 negotiation pending ro reset to 0 31:2 reserved ro reset to 0 7.4.123 reserved registers ? offset 16ch ? 300h 7.4.124 extra gpi/gpo data and control register ? offset 304h bit function type description 3:0 extra gpo rwc gpo [3:0], write 1 to clear reset to 0 7:4 extra gpo rws gpo [3:0], write 1 to set reset to 0 11:8 extra gpo enable rwc gpo [3 :0] enable, write 1 to clear reset to 0 15:12 extra gpo enable rws gpo [3:0] enable, write 1 to set reset to 0 19:16 extra gpi ro extra gpi [3:0] data register reset to 0 31:20 reserved ro reset to 0 7.4.125 reserved registers ? offset 308h ? 30ch 7.4.126 replay and acknowledge latency timers ? offset 310h bit function type description 11:0 replay timer rw replay timer reset to 0 12 replay timer enable rw replay timer enable reset to 0 15:13 reserved ro reset to 0 29:16 acknowledge latency timer rw acknowledge latency timer reset to 0 30 acknowledge latency timer enable ro acknowledge latency timer enable reset to 0 31 reserved ro reset to 0 7.4.127 reserved registers ? offset 314h ? ffch
pi7c9x110 pcie-to-pci reversible bridge page 73 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5 pci configuration register s for non-transparent bridge mode the following section describes the co nfiguration space when the device is in non-transparent bridge mode. the descriptions for different register type are listed as follow: register type descriptions ro read only ros read only and sticky rw read/write rwc read/write ?1? to clear rws read/write and sticky rwcs read/write ?1? to clear and sticky 7.5.1 vendor id ? offset 00h bit function type description 15:0 vendor id ro identifies pericom as the vendor of this device. returns 12d8h when read. 7.5.2 device id ? offset 00h bit function type description 31:16 device id ro identifies this device as the pi7c9x110. returns e110 when read. 7.5.3 command register ? offset 04h bit function type description 0 i/o space enable rw 0: ignore i/ o transactions on the primary interface 1: enable response to memory tr ansactions on the primary interface reset to 0 1 memory space enable rw 0: ignore memory read transactions on the primary interface 1: enable memory read tran sactions on the primary interface reset to 0 2 bus master enable rw 0: do not initiate memo ry or i/o transactions on the primary interface and disable response to memory and i/o tr ansactions on the secondary interface 1: enable the bridge to operate as a master on the primary interfaces for memory and i/o transactions forwar ded from the secondary interface. reset to 0 3 special cycle enable ro 0: pi7c9x110 does not re spond as a target to special cycle transactions, so this bit is defined as read-only and must return 0 when read reset to 0 4 memory write and invalidate enable ro 0: pi7c9x110 does not originate a memory write and invalidate transaction. implements this bit as read-only and returns 0 when read (unless forwarding a transaction for another master). reset to 0 5 vga palette snoop enable ro / rw this bit applies to reverse bridge only. 0: ignore vga palette access on the primary 1: enable positive decoding response to vga palette writes on the primary interface with i/o address bits ad [9 :0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa alias; ad [15:0] ar e not decoded and may be any value) reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 74 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 6 parity error response enable rw 0: may ignore any parity error that is detected and take its normal action 1: this bit if set, enables the setting of master data par ity error bit in the status register when poisoned tlp received or parity error is detected and takes its normal action reset to 0 7 wait cycle control ro wait cycle control not supported reset to 0 8 serr_l enable bit rw 0: disable 1: enable pi7c9x110 in forward bri dge mode to report non-fatal or fatal error message to the root complex. also , in reverse bridge mode to assert serr_l on the primary interface reset to 0 9 fast back-to-back enable ro fast back-to-back enable not supported reset to 0 10 interrupt disable ro / rw this bit applies to reverse bridge only. 0: inta_l, intb_l, intc_l, and intd_l can be asserted on pci interface 1: prevent inta_l, intb_l, intc_l, and intd_l from being asserted on pci interface reset to 0 15:11 reserved ro reset to 00000 7.5.4 primary status register ? offset 04h bit function type description 18:16 reserved ro reset to 000 19 primary interrupt status ro 0: no intx inte rrupt message request pe nding in pi7c9x110 primary 1: intx interrupt message reque st pending in pi7c9x110 primary reset to 0 20 capability list capable ro 1: pi7c9x110 supports the capability list (offset 34h in the pointer to the data structure) reset to 1 21 66mhz capable ro this bit applies to reverse bridge only. 1: 66mhz capable reset to 0 when forward bridge or 1 when reverse bridge. 22 reserved ro reset to 0 23 fast back-to-back capable ro this bit applies to reverse bridge only. 1: enable fast back-to-back transactions reset to 0 when forward bridge or 1 when reverse bridge with primary bus in pci mode
pi7c9x110 pcie-to-pci reversible bridge page 75 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 24 master data parity error detected rwc bit set if its parity erro r enable bit is set and eith er of the conditions occurs on the primary: forward bridge ? ? receives a completion marked poisoned ? poisons a write request reverse bridge ? ? detected parity error when receivi ng data or split response for read ? observes p_perr_l asserted when sending data or receiving split response for write ? receives a split completion message indicating data parity error occurred for non-posted write reset to 0 26:25 devsel_l timing (medium decode) ro these bits apply to reverse bridge only. 00: fast devsel_l decoding 01: medium devsel_l decoding 10: slow devsel_l decoding 11: reserved reset to 00 when forward bridge or 01 when reverse bridge. 27 signaled target abort rwc forward bridge ? this bit is set when pi7c9x110 completes a request using completer abort status on the primary reverse bridge ? this bit is set to indicate a target abort on the primary reset to 0 28 received target abort rwc forward bridge ? this bit is set when bridge receives a completion with completer abort completion status on the primary reverse bridge ? this bit is set when pi7c9x110 detects a target abort on the primary reset to 0 29 received master abort rwc forward bridge ? this bit is set when pi7c9x110 r eceives a completion with unsupported request completion status on the primary reverse bridge ? this bit is set when pi7c9x110 detects a master abort on the primary 30 signaled system error rwc forward bridge ? this bit is set when pi7c9x110 sends an err_fatal or err_non_fatal message on the primary reverse bridge ? this bit is set when pi7c9x110 asserts serr_l on the primary reset to 0 31 detected parity error rwc forward bridge ? this bit is set when poisoned tlp is detected on the primary reverse bridge ? this bit is set when address or data parity error is detected on the primary reset to 0 7.5.5 revision id register ? offset 08h bit function type description 7:0 revision ro reset to 00000002h 7.5.6 class code register ? offset 08h
pi7c9x110 pcie-to-pci reversible bridge page 76 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 15:8 programming interface ro subtractive d ecoding of pci-pci br idge not supported reset to 00000000 23:16 sub-class code ro sub-class code 10000000: other bridge reset to 10000000 31:24 base class code ro base class code 00000110: bridge device (transparent mode ) reset to 00000110 (transparent mode ) 7.5.7 cache line size register ? offset 0ch bit function type description 1:0 reserved ro bit [1:0] not supported reset to 00 2 cache line size rw 1: cache line size = 4 double words reset to 0 3 cache line size rw 1: cache line size = 8 double words reset to 0 4 cache line size rw 1: cache line size = 16 double words reset to 0 5 cache line size rw 1: cache line size = 32 double words reset to 0 7:6 reserved ro bit [7:6] not supported reset to 00 7.5.8 primary latency timer register ? offset 0ch bit function type description 15:8 primary latency timer ro / rw 8 bits of primary latency timer in pci forward bridge ? ro with reset to 00h reverse bridge ? rw with reset to 00h in pci mode 7.5.9 primary header type register ? offset 0ch bit function type description 22:16 other bridge configuration (non-transparent mode ) ro type-0 header format configuration (10-3fh) reset to 0000000 (non-transparent mode ) 23 single function device ro 0: indicates single function device reset to 0 31:24 reserved ro reset to 00h 7.5.10 primary csr and memory 0 base address register ? offset 10h bit function type description 0 space indicator ro 0: memory space 1: io space
pi7c9x110 pcie-to-pci reversible bridge page 77 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0 31:12 base address rw/ro the size and type of th is base address register are defined from downstream memory 0 setup register (offset 9ch), which can be initialized by eeprom (i2c) or sm bus or local processor. the range of this register is from 4kb to 2gb. the lower 4kb if this address reange map to the pi7c9x110 csrs into memory space. the remaining space is this range above 4kb, if any, specifies a range for forwarding downstream memory transactions. pi7x9x110 uses downstream memory 0 translated base register (offset 98h) to formulate direct address translation. if a bit in the setup register is set to one, then the co rrespondent bit of this register will be changed to rw. reset to 00000h 7.5.11 primary csr i/o base address register ? offset 14h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 1 7:1 reserved ro reset to 0 31:8 base address ro/rw this base address regi ster maps to pi7c9x110 primary io space. the maximum size is 256 bytes. reset to 00000000h 7.5.12 downstream i/o or memory 1 base address register ? offset 18h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0 31:12 base address rw/ro the size and type of th is base address register are defined from downstream io or memory 1 setup re gister (offset ach), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup register to di sable this register. the range of this register is from 4kb to 2gb for memory space or from 64b to 256b for io space. pi7x9x110 uses downstream io or memory 1 translated base register (offset a8h) to formulate direct address translation. if a bit in the setu p re g ister is set to one, then the corres p ondent bit of this re g ister will be
pi7c9x110 pcie-to-pci reversible bridge page 78 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description changed to rw. reset to 00000h 7.5.13 donwstream memory 2 base address register ? offset 1ch bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01, 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0 31:12 base address rw/ro the size and type of th is base address register are defined from downstream memory 2 setup register (csr offset 00ch), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup register to di sable this register. the range of this register is from 4kb to 2gb for memory space. pi7x9x110 uses downstream memory 2 translated base register (csr offset 008h) to formulate direct address translation. if a bit in the setup register is set to one, then the correspondent bit of this register will be changed to rw. reset to 00000h 7.5.14 downstream memory 3 base address register ? offset 20h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0 31:12 base address rw/ro the size and type of th is base address register are defined from downstream memory 3 setup register (csr offset 014h), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup registers (csr offset 014h and 018h) to disable this register. the range of this register is from 4kb to 9eb for memory space. pi7c9x110 uses memory 3 translated ba se register (csr offset 010h) to formulate direct address translati on when 32-bit addressing programmed. when 64-bit addressing programmed, no addr ess translation is performed. if a bit in the setup register is set to one, then the correspondent bit of this register will be changed to rw. reset to 00000h
pi7c9x110 pcie-to-pci reversible bridge page 79 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.15 downstream memory 3 upper base address register ? offset 24h bit function type description 31:0 base address ro/rw the size of this base addr ess register is defined from downstream memory 3 upper 32-bit setup register (csr offs et 018h), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup registers (csr offset 018h) to disable this register. this register defines the upper 32 bits of a memo ry range for downstream forwarding memory. if a bit in the setup register is set to one, then the correspondent bit of this register will be changed to rw. reset to 00000000h 7.5.16 reserved register ? offset 28h 7.5.17 subsytem id and subsystem vendor id register ? offset 2ch bit function type description 15:0 subsystem vendor id ro identify the ve ndor id for add-in card or subsystem reset to 0000h 31:16 subsystem id ro identify the vendor speci fic device id for add-in card or subsystem reset to 0000h 7.5.18 reserved register ? offset 30h 7.5.19 capability pointer ? offset 34h bit function type description 31:8 reserved ro reset to 0 7:0 capability pointer ro capability pointer to 80h reset to 80h 7.5.20 expansion rom base address register ? offset 38h bit function type description 31:0 expansion rom base address ro expansion rom not supported. reset to 00000000h 7.5.21 primary interrupt line register ? offset 3ch bit function type description 7:0 primary interrupt line rw these bits apply to reverse bridge only. for initialization code to program to tell which input of the interrupt controller the pi7c9x110?s inta_l in connected to. reset to 00000000 7.5.22 primary interrupt pin register ? offset 3ch bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 80 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 15:8 primary interrupt pin ro these bits apply to reverse bridge only. designates interrupt pin inta_l, is used reset to 00h when forward mode or 01h when reverse mode. 7.5.23 primary minimum grant register ? offset 3ch bit function type description 23:16 primary minimum grant ro this register is valid only in reverse bridge mode. it specifies how long of a burst period that pi7c9x110 needs on the primary bus in the units of ? microseconds. reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 81 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.24 primary maximum latency time register ? offset 3ch bit function type description 31:24 primary maximum latency timer ro this register is valid only in reverse bridge mode. it speci fies how often that pi7c9x110 needs to gain access to the primary bus in units of ? microseconds. reset to 0 7.5.25 pci data buffering co ntrol register ? offset 40h bit function type description 0 secondary internal arbiter?s park function rw 0: park to the last master 1: park to pi7c9x110 secondary port reset to 0 1 memory read prefetching dynamic control disable rw 0: enable memory read prefetchi ng dynamic control for pci to pcie read 1: disable memory read prefetching dynamic control for pci to pcie read reset to 0 2 completion data prediction control rw 0: enable completion data pr ediction for pci to pcie read. 1: disable completion data prediction reset to 0 3 reserved ro reset to 0 5:4 pci read multiple prefetch mode rw 00: one cache line prefetch if me mory read multiple address is in prefetchable range at the pci interface 01: full prefetch if address is in pref etchable range at pci interface, and the pi7c9x110 will keep remaining data afte r it disconnects the external master during burst read with read multiple command until the discard timer expires 10: full prefetch if address is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data afte r the read multiple is terminated either by an external master or by the pi7c9x110, until the discard time expires reset to 10 7:6 pci read line prefetch mode rw 00: once cache line prefetch if memory read address is in prefetchable range at pci interface 01: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data afte r it is disconnected by an external master during burst read with read lin e command, until discard timer expires 10: full prefetch if memory read line a ddress is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x110 will keep remaining data after the read line is te rminated either by an external master or by the pi7c9x110, until the discard timer expires reset to 00
pi7c9x110 pcie-to-pci reversible bridge page 82 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 9:8 pci read prefetch mode rw 00: one cache line prefet ch if memory read address is in prefetchable range at pci interface 01: reserved 10: full prefetch if memory read addr ess is in prefetchable range at pci interface 11: disconnect on the first dword reset to 00 10 pci special delayed read mode enable rw 0: retry any master at pci bus that repeats its transaction with command code changes. 1: allows any master at pci bus to change memory command code (mr, mrl, mrm) after it has received a retr y. the pi7c9x110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. reset to 0 11 reserved ro reset to 0 14:12 maximum memory read byte count rw maximum byte count is used by the pi7c9x110 when generating memory read requests on the pcie link in response to a memory read initiated on the pci bus and bit [9:8], bit [7:6], and bit [5:4] are set to ?full prefetch?. 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes reset to 000 7.5.26 chip control 0 register ? offset 40h bit function type description 15 flow control update control rw 0: flow control is updated for every two credits available 1: flow control is updated for every on credit available reset to 0 16 pci retry counter status rwc 0: the pci retr y counter has not expired since the last reset 1: the pci retry counter has expired since the last reset reset to 0 18:17 pci retry counter control rw 00: no expiration limit 01: allow 256 retries before expiration 10: allow 64k retries before expiration 11: allow 2g retrie s before expiration reset to 00 19 pci discard timer disable rw 0: enable the pci di scard timer in conjunction with bit [27] offset 3ch (bridge control register) 1: disable the pci discard timer in conjunction with bit [27] offset 3ch (bridge control register) reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 83 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 20 pci discard timer short duration rw 0: use bit [24] offset 3ch for forward bridge or bit [25] offset 3ch for reverse bridge to indicate how many pci clocks should be allowed before the pci discard timer expires 1: 64 pci clocks allowed before the pci discard timer expires reset to 0 22:21 configuration request retry timer counter value control rw 00: timer expires at 25us 01: timer expires at 0.5ms 10: timer expires at 5ms 11: timer expires at 25ms reset to 01 23 delayed transaction order control rw 0: enable out-of-order capability between delayed transactions 1: disable out-of-order capability between delayed transactions reset to 0 25:24 completion timer counter value control rw 00: timer expires at 50us 01: timer expires at 10ms 10: timer expires at 50ms 11: timer disabled reset to 01 26 isochronous traffic support enable rw 0: all memory transactions from pci to pcie will be mapped to tc0 1: all memory transactions from pci to pcie will be mapped to traffic class defined in bit [29:27] of offset 40h. reset to 0 29:27 traffic class used for isochronous traffic rw reset to 001 30 serial link interface loopback enable rw / ro 0: normal mode 1: enable serial link interface loopb ack mode (tx to rx) if tm0=low, tm1=high, tm2=high, msk_in=high, revrsb=high. pci transaction from pci bus will loop back to pci bus ro for forward bridge reset to 0 31 primary configuration access lockout ro / rw 0: pi7c9x110 configuration space can be accessed from both interfaces 1: pi7c9x110 configuration space can only be accessed from the secondary interface. primary bus accessed receives completion with crs status for forward bridge, or target retry for reverse bridge reset to 0 if tm0 is low 7.5.27 secondary command register ? offset 44h bit function type description 0 i/o space enable rw 0: ignore i/o transactions on the secondary interface 1: enable response to memory tr ansactions on the secondary interface reset to 0 1 memory space enable rw 0: ignore memory read transactions on the secondary interface 1: enable memory read trans actions on the secondary interface reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 84 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 2 bus master enable rw 0: do not initiate memory or i/o transactions on the secondary interface and disable response to memory and i/o tr ansactions on the secondary interface 1: enable the pi7c9x110 to operate as a master on the secondary interfaces for memory and i/o transactions forwarded from the secondary interface. reset to 0 3 special cycle enable ro 0: bridge does not respond as a target to special cycle transactions, so this bit is defined as read-only and must return 0 when read reset to 0 4 memory write and invalidate enable ro 0: pi7c9x110 does not originate a memory write and invalidate transaction. implements this bit as read-only and returns 0 when read (unless forwarding a transaction for another master). reset to 0 5 vga palette snoop enable ro 0: ignor e vga palette snoop access on the secondary reset to 0 6 parity error response enable rw 0: may ignore any parity error that is detected and take its normal action 1: this bit if set, enables the setting of master data par ity error bit in the status register when poisoned tlp received or parity error is detected and takes its normal action reset to 0 7 wait cycle control ro wait cycle control not supported reset to 0 8 secondary serr_l enable bit rw 0: disable 1: enable pi7c9x110 in forward bridge mode to report non-fatal or fatal error message to the root complex. al so, in reverse bridge mode to assert serr_l on the secondary interface reset to 0 9 fast back-to-back enable ro fast back-to-back enable not supported reset to 0 10 secondary interrupt disable ro / rw 0: intx interrupt messages can be generated 1: prevent intx messages to be gene rated and any asserted intx interrupts will be released. reset to 0 15:11 reserved ro reset to 00000 7.5.28 secondary status register ? offset 44h bit function type description 18:16 reserved ro reset to 000 19 secondary interrupt status ro 0: no intx inte rrupt message request pendi ng in pi7c9x110 secondary 1: intx interrupt message reque st pending in pi7c9x110 secondary reset to 0 20 capability list capable ro 1: pi7c9x110 supports the capability list (offset 34h in the pointer to the data structure) reset to 1 21 66mhz capable ro this bit applies to forward bridge only. 1: 66mhz capable reset to 0 when reverse bridge or 1 when forward bridge. 22 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 85 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 23 fast back-to-back capable ro this bit applies to forward bridge only. 1: enable fast back-to-back transactions reset to 0 when reverse bridge or 1 wh en forward bridge with secondary bus in pci mode 24 master data parity error detected rwc bit set if its parity erro r enable bit is set and eith er of the conditions occurs on the secondary: reverse bridge ? ? receives a completion marked poisoned ? poisons a write request forward bridge ? ? detected parity error when receivi ng data or split response for read ? observes p_perr_l asserted when sending data or receiving split response for write ? receives a split completion message indicating data parity error occurred for non-posted write reset to 0 26:25 devsel_l timing (medium decode) ro these bits apply to forward bridge only. 00: fast devsel_l decoding 01: medium devsel_l decoding 10: slow devsel_l decoding 11: reserved reset to 00 when reverse bridge or 01 when forward bridge. 27 signaled target abort rwc reverse bridge ? this bit is set when pi7c9x110 completes a request using completer abort status on the secondary forward bridge ? this bit is set to indicate a target abort on the secondary reset to 0 28 received target abort rwc reverse bridge ? this bit is set when bridge receives a completion with completer abort completion status on the secondary forward bridge ? this bit is set when pi7c9x110 detects a target abort on the secondary reset to 0 29 received master abort rwc reverse bridge ? this bit is set when pi7c9x110 r eceives a completion with unsupported request completion status on the secondary forward bridge ? this bit is set when pi7c9x110 detects a master abort on the secondary 30 signaled system error rwc reverse bridge ? this bit is set when pi7c9x110 sends an err_fatal or err_non_fatal message on the secondary forward bridge ? this bit is set when pi7c9x110 asserts serr_l on the secondary reset to 0 31 detected parity error rwc reverse bridge ? this bit is set when poisoned tlp is detected on the secondary forward bridge ? this bit is set when address or data pa rity error is detected on the secondary reset to 0 7.5.29 arbiter enable register ? offset 48h
pi7c9x110 pcie-to-pci reversible bridge page 86 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 0 enable arbiter 0 rw 0: disable arb itration for internal pi7c9x110request 1: enable arbitration for internal pi7c9x110 request reset to 1 1 enable arbiter 1 rw 0: disable arbitration for master 1 1: enable arbitration for master 1 reset to 1 2 enable arbiter 2 rw 0: disable arbitration for master 2 1: enable arbitration for master 2 reset to 1 3 enable arbiter 3 rw 0: disable arbitration for master 3 1: enable arbitration for master 3 reset to 1 4 enable arbiter 4 rw 0: disable arbitration for master 4 1: enable arbitration for master 4 reset to 1 5 enable arbiter 5 rw 0: disable arbitration for master 5 1: enable arbitration for master 5 reset to 1 6 enable arbiter 6 rw 0: disable arbitration for master 6 1: enable arbitration for master 6 reset to 1 7 enable arbiter 7 rw 0: disable arbitration for master 7 1: enable arbitration for master 7 reset to 1 8 enable arbiter 8 rw 0: disable arbitration for master 8 1: enable arbitration for master 8 reset to 1 7.5.30 arbiter mode register ? offset 48h bit function type description 9 external arbiter bit ro 0: enable in ternal arbiter (if cfn_l is tied low) 1: use external arbiter (if cfn_l is tied high) reset to 0/1 according to what cfn_l is tied to 10 broken master timeout enable rw 0: broken master timeout disable 1: this bit enables the internal arb iter to count 16 pci bus cycles while waiting for frame_l to become activ e when a device?s pci bus gnt is active and the pci bus is idle. if the broken master timeout expires, the pci bus gnt for the device is de-asserted. reset to 0 11 broken master refresh enable rw 0: a broken master will be ignored forever after de-asserting its req_l for at least 1 clock 1: refresh broken master state after a ll the other masters have been served once reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 87 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 19:12 arbiter fairness counter rw 08h: these bits are the initialization value of a count er used by the internal arbiter. it controls the number of pc i bus cycles that the arbiter holds a device?s pci bus gnt active after detecting a pci bus req_l from another device. the counter is reloaded whenever a new pci bus gnt is asserted. for every new pci bus gnt, the counter is armed to decrement when it detects the new fall of frame_l. if the arbiter fairness counter is set to 00h, the arbiter will not remove a device?s pci bus gnt until the device has de- asserted its pci bus req. reset to 08h 20 gnt_l output toggling enable rw 0: gnt_l not de-asserted afte r granted master assert frame_l 1: gnt_l de-asserts for 1 clock after 2 cl ocks of the granted master asserting frame_l reset to 0 21 reserved ro reset to 0 7.5.31 arbiter priority register ? offset 48h bit function type description 22 arbiter priority 0 rw 0: low prio rity request to internal pi7c9x110 1: high priority request to internal pi7c9x110 reset to 1 23 arbiter priority 1 rw 0: low priority request to master 1 1: high priority request to master 1 reset to 0 24 arbiter priority 2 rw 0: low priority request to master 2 1: high priority request to master 2 reset to 0 25 arbiter priority 3 rw 0: low priority request to master 3 1: high priority request to master 3 reset to 0 26 arbiter priority 4 rw 0: low priority request to master 4 1: high priority request to master 4 reset to 0 27 arbiter priority 5 rw 0: low priority request to master 5 1: high priority request to master 5 reset to 0 28 arbiter priority 6 rw 0: low priority request to master 6 1: high priority request to master 6 reset to 0 29 arbiter priority 7 rw 0: low priority request to master 7 1: high priority request to master 7 reset to 0 30 arbiter priority 8 rw 0: low priority request to master 8 1: high priority request to master 8 reset to 0 31 reserved ro reset to 0 7.5.32 secondary cache line size register ? offset 4ch bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 88 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 1:0 reserved ro 00: cache line size of 1 dw and 2 dw are not supported reset to 00 2 cache line size rw 1: cache line size = 4 double words reset to 0 3 cache line size rw 1: cache line size = 8 double words reset to 0 4 cache line size rw 1: cache line size = 16 double words reset to 0 5 cache line size rw 1: cache line size = 32 double words reset to 0 7:6 reserved ro bit [7:6] not supported reset to 00 7.5.33 secondary latency time register ? offset 4ch bit function type description 15:8 secondary latency timer ro / rw 8 bits of secondary latency timer in pci reverse bridge ? ro with reset to 00h forward bridge ? rw with reset to 00h in pci mode 7.5.34 secondary header type register ? offset 4ch bit function type description 22:16 other bridge configurati on ro type-0 header format configuration (10 ? 3fh) reset to 0000000 23 single function device ro 0: indicates single function device reset to 0 31:24 reserved ro reset to 00h 7.5.35 secondary csr and memory 0 ba se address register ? offset 50h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 89 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31:12 base address rw/ro the size and type of this base address register ar e defined from upstream memory 0 setup register (offset e 4h), which can be initialized by eeprom (i2c) or sm bu s or local processor. the range of this register is from 4kb to 2gb. the lower 4kb if this address reange map to the pi7c9x110 csrs into memory space. the remaining space is this range above 4kb, if any, specifies a range for forwarding upstream memory transactions. pi7x9x110 uses upstream memory 0 translated base register (offset e0h) to formulate direct address translation. if a bit in the setup register is set to one, then the corr espondent bit of this register will be changed to rw. reset to 00000h 7.5.36 secondary csr i/o base address register ? offset 54h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 1 7:1 reserved ro reset to 0 31:8 base address ro/rw this base address register maps to pi7c9x110 secondary io space. the maximum size is 256 bytes. reset to 00000000h 7.5.37 upstream i/o or memory 1 ba se address register ? offset 58h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 5:4 reserved ro reset to 0 31:6 base address rw/ro the size and type of this base address register ar e defined from upstream io or memory 1 setup register (offs et ech), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup register to disable this regist er. the range of this register is from 4kb to 2gb for memory space or from 64b to 256b for io space. pi7x9x110 uses upstream io or memory 1 translated base register (offset e8h) to formulate direct address translati on. if a bit in the setup register is set to one, then the correspondent bit of this register will be changed to rw. reset to 00000h 7.5.38 upstream memory 2 base address register ? offset 5ch bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 90 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 2:1 address type ro 00: 32- bit address decode range 01, 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 13:4 reserved ro reset to 0 31:14 base address rw/ro this base address regist er defines the address range for upstream memory transactions. pi7c9x110 uses a lookup ta ble to do the address translation. the address range of this register is from 16kb to 2gb in memory space. the address range is divided into 64 page s. the size of each page is defined by memory address forwarding control register (offset 6ah), which is initialized by eeprom (i2c) or sm bus or local processor. writing a zero to the bit [0] of the look up table entry can disable the corresponding page of this register (csr offset 1ffh: 100h). the number of writeable bit may cha nge depending on the page size setup. reset to 00000h 7.5.39 upstream memory 3 base address register ? offset 60h bit function type description 0 space indicator ro 0: memory space 1: io space reset to 0 2:1 address type ro 00: 32- bit address decode range 01: 64-bit address decode range 10 and 11: reserved reset to 00 3 prefetchable control ro 0: memory space is non-prefetchable 1: memory space is prefetchable reset to 0 11:4 reserved ro reset to 0 31:12 base address rw/ro the size and type of this base address register ar e defined from upstream memory 3 setup register (csr offs et 034h), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup registers (csr offset 034h and 038h) to disable this register. the range of this register is from 4kb to 9eb for memory space. pi7c9x110 uses this register and the upstream memory 3 upper base address register when 64-bit addressing programmed (bit [21] of offset 68h). when 64-bit addressing is disabled, no address tran slation is performed. all 64-bit address transactions on the seconda ry interface falling outside of the downstream memory 3 address range are forwarded upstream. reset to 00000h
pi7c9x110 pcie-to-pci reversible bridge page 91 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.40 upstream memory 3 upper ba se address register ? offset 64h bit function type description 31:0 base address ro/rw the size of this base addr ess register is defined from upstream memory 3 upper 32-bit setup register (csr offs et 038h), which can be initialized by eeprom (i2c) or sm bus or local processor. writing a zero to bit [31] of the setup registers (csr offset 038h) to disable this register. this register defines the upper 32 bits of a memory range for upstream forwarding memory. pi7c9x110 uses this register and the upstream memory 3 base address register when 64-bit addre ssing programmed (bit [21] of offset 68h). when 64-bit addressing is disa bled, no address translation is performed. all 64-bit address transa ctions on the secondary interface falling outside of the downstream memory 3 address range are forwarded upstream. reset to 00000000h 7.5.41 express transmitter/receiver register ? offset 68h bit function type description 1:0 nominal driver current control rw 00: 20ma 01: 10ma 10: 28ma 11: reserved reset to 00 5:2 driver current scale multiple control rw 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current reset to 0000 11:8 driver de-emphasis level control rw 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db reset to 1000
pi7c9x110 pcie-to-pci reversible bridge page 92 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 13:12 transmitter termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00 15:14 receiver termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00 7.5.42 memory address forwarding control register ? offset 68h bit function type description 19:16 lookup table page size rw if bit [20] of offset 68h is low, then 0000: disable upstream memory 2 base address register 0001: 256 bytes 0010: 512 bytes 0011: 1k bytes 0100: 2k bytes 0101: 4k bytes 0110: 8k bytes 0111: 16k bytes 1000: 32k bytes 1001: 64k bytes 1010: 128k bytes 1011: 256k bytes 1100: 512k bytes 1101: 1m bytes 1110: 2m bytes 1111: 4m bytes if bit [20] of offset 68h is high, then 0000: disable upstream memory 2 base address register 0001: 8m bytes 0010: 16m bytes 0011: 32m bytes 01xx: disable upstream memory 2 base address register 1xxx: disable upstream memory 2 base address register reset to 0h 20 lookup table page size extension rw 0: normal lookup table page size 1: coarse lookup table page size reset to 0 21 upstream 64-bit address range enable rw 0: any 64-bit address transactions on secondary interface falling outside of downstream memory 3 address range are forwarded upstream 1: enable 64-bit address transaction forwarding upstream based on upstream memory 3 address range w ithout address translation reset to 0 29:22 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 93 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.43 upstream memory write fragment control register ? offset 68h bit function type description 31:30 memory write fragment control rw upstream memory write fragment control 00: fragment at 32-byte boundary 01: fragment at 64-byte boundary 1x: fragement at 128-byte boundary reset to 10h 7.5.44 subsystem vendor id register ? offset 6ch bit function type description 15:0 subsystem vendor id ro subsystem vendor id iden tifies the particular add-in card or subsystem. reset to 00h 7.5.45 subsystem id register ? offset 6ch bit function type description 31:16 subsystem id ro subsystem id identifies the particular add-in card or subsystem. reset to 00h 7.5.46 eeprom autoload control/status register ? offset 70h bit function type description 0 initiate eeprom read or write cycle rw this bit will be reset to 0 afte r the eeprom operation is finished. 0: eeprom autoload disabled 0 -> 1: starts the eeprom read or write cycle reset to 0 1 control command for eeprom rw 0: read 1: write reset to 0 2 eeprom error ro 0: eeprom acknowledge is always received during the eeprom cycle 1: eeprom acknowledge is not received during eeprom cycle reset to 0 3 eprom autoload complete status ro 0: eeprom autoload is not successfully completed 1: eeprom autoload is successfully completed reset to 0 5:4 eeprom clock frequency control rw where pclk is 125mhz 00: pclk / 4096 01: pclk / 2048 10: pclk / 1024 11: pclk / 128 reset to 00 6 eeprom autoload control rw 0: enable eeprom autoload 1: disable eeprom autoload reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 94 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 7 fast eeprom autoload control rw 0: normal speed of eeprom autoload 1: increase eeprom autoload by 32x reset to 0 8 eeprom autoload status ro 0: eeprom autoload is not on going 1: eeprom autoload is on going reset to 0 15:9 eeprom word address rw eeprom word address for eeprom cycle reset to 0000000 31:16 eeprom data rw eeprom data to be written into the eeprom reset to 0000h 7.5.47 reserved register ? offset 74h 7.5.48 bridge control and st atus register ? offset 78h bit function type description 1:0 reserved ro reset to 00 2 serr_l forward enable rw/ro 0: disable the forwarding of serr_l to err_fatal and err_nonfatal 1: enable the forwarding of serr_l to err_fatal and err_nonfatal reset to 0 (forward bridge) ro bit for reverse bridge 3 secondary interface reset rw 0: do not force the assertion of reset_l on secondary pci bus in forward bridge mode, or do not ge nerate a hot reset on the pci express link in reverse bridge mode 1: force the assertion of reset_l on secondary pci bus in forward bridge mode, or generate a hot reset on the pc i express link in reverse bridge mode reset to 0 5:4 vga enable rw 00: vga memory and i/o tr ansactions on the primary and secondary interfaces are ignored, unless decoded by other mechanism 01: vga memory and i/o transactions on the primary interface are forwarded to secondary interface w ithout address translation, but vga transactions on secondary interface are ignored 10: vga memory and i/o transacti ons on the secondary interface are forwarded to primary interface wit hout address translation, but vga transactions on primary interface are ignored reset to 00 6 vga 16-bit decode rw 0: execute 10- bit address decodes on vga i/o accesses 1: execute 16-bit address decode on vga i/o accesses reset to 0 7 master abort mode rw 0: do not report mast er aborts (return ffffffffh on reads and discards data on write) 1: report master abort by signaling target abort if possible or by the assertion of serr_l (if enabled). reset to 0 8 primary master timeout rw 0: primar y discard timer counts 215 pci clock cycles 1: primary discard timer counts 210 pci clock cycles forward bridge ? bit is ro and ignored by pi7c9x110 reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 95 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 9 secondary master timeout rw 0: seconda ry discard timer counts 215 pci clock cycles 1: secondary discard time r counts 210 pci clock cycles reverse bridge ? bit is ro and ignored by pi7c9x110 reset to 0 10 master timeout status rwc bit is set when the discard timer expires and a delayed completion is discarded at the pci interface for the forward or reverse bridge reset to 0 11 discard timer serr_l enable rw bit is set to enable to gene rate err_nonfatal or err_fatal for forward bridge, or assert serr_l for reverse bridge as a result of the expiration of the discard timer. reset to 0 7.5.49 gpio data and control register ? offset 78h bit function type description 15:12 gpio output write-1-to- clear rw reset to 0h 19:16 gpio output write-1-to-set rw reset to 0h 23:20 gpio output enable write- 1-to-clear rw reset to 0h 27:24 gpio output enable write- 1-to-set rw reset to 0h 31:28 gpio input data register ro reset to 0h 7.5.50 secondary interrupt line register ? offset 7ch bit function type description 7:0 secondary interrupt line rw these bits apply to forward bridge only . for initialization code to program to tell which input of the interrupt controller the bridge?s inta_l in connected to. reset to 00000000 7.5.51 secondary interrupt pin register ? offset 7ch bit function type description 15:8 secondary interrupt pin ro these bits apply to forward bridge only. 00000001: designates interrupt pin inta_l is used reset to 00h when reverse mode or 01h when forward mode. 7.5.52 secondary minimum grant register ? offset 7ch bit function type description 23:16 secondary minimum grant ro this re gister is valid only in forward bridge mode. it specifies how long of a burst period that pi7c9x110 needs on the secondary bus in the units of ? microseconds. reset to 0 7.5.53 secondary maximum latency timer register ? offset 7ch bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 96 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31:24 secondary maximum latency timer ro this register is valid only in forward bridge mode. it speci fies how often that pi7c9x110 needs to gain access to the primary bus in units of ? microseconds. reset to 0 7.5.54 capability id register ? offset 80h bit function type description 7:0 capability id ro capability id reset to 07h 7.5.55 next capability pointer register ? offset 80h bit function type description 15:8 next capability pointer ro point to power management reset to 90h 7.5.56 secondary status register ? offset 80h bit function type description 16 64-bit device on secondary bus interface ro 64-bit not supported reset to 0 17 133mhz capable ro when this bit is 1, pi7c9x110 is 133mhz capable on its secondary bus interface reset to 1 in forward bridge mode or 0 in reverse bridge mode 18 split completion discarded ro / rwc this bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode when this is set to 1, a split completion has been discarded by pi7c9x110 at secondary bus because the requester did not accept the split completion transaction reset to 0 19 unexpected split completion rwc this bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode when this is set to 1, an unexpected split completion has been received with the requester id equaled to the secondary bus number, device number, and function number at the pi7x9x110 secondary bus interface reset to 0 20 split completion overrun rwc when this bit is set to 1, a split completion has been terminated by pi7c9x110 with either a retry or disc onnect at the next adb due to the buffer full condition reset to 0 21 split request delayed rwc when this bit is set to 1, a split request is delayed because pi7c9x110 is not able to forward the split request tran saction to its secondary bus due to insufficient room with in the limit specified in the split transaction commitment limit field of the downstream split transaction control register reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 97 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 24:22 secondary clock fre quency ro these bits are only meaningful in forward bridge mode. in reverse bridge mode, all three bits are set to zero. 000: conventional pci mode (minim um clock period not applicable) 001: 66mhz (minimum clock period is 15ns) 010: 100 to 133mhz (minimum clock period is 7.5ns) 011: reserved 1xx: reserved reset to 000 31:25 reserved ro 0000000 7.5.57 bridge status register ? offset 84h bit function type description 2:0 function number ro function number (ad [10: 8] of a type 0 configuration transaction) reset to 000 7:3 device number ro device number (ad [15:11] of a type 0 configuration transaction) is assigned to the pi7c9x110 by the connection of system hardware. each time the pi7c9x110 is addressed by a configura tion write transaction, the bridge updates this register with the contents of ad [15:11] of the address phase of the configuration transaction, regardle ss of which register in the pi7c9x110 is addressed by the transaction. the pi7c9x110 is addressed by a configuration write tran saction if all of the following are true: ? the transaction uses a configuration write command ? idsel is asserted during the address phase ? ad [1:0] are 00 (type o configuration transaction) ? ad [10:8] of the configuration addr ess contain the appropriate function number reset to 11111 15:8 bus number ro additional address from wh ich the contents of the primary bus number register on type 1 configuration space header is read. the pi7c9x110 uses the bus number, device number, and function number fields to create a completer id when responding with a split completion to a read of an internal pi7c9x110 register. these fields are al so used for cases when one interface is in conventional pci mode. reset to 11111111 16 64-bit device on primary bus interface ro 64-bit not supported reset to 0 17 133mhz capable ro when this bit is 1, pi7c9x110 is 133mhz capable on its primary bus interface reset to 0 in forward bridge mode or 1 in reverse bridge mode 18 split completion discarded ro / rwc this bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode when this is set to 1, a split completion has been discarded by pi7c9x110 at primary bus because the requester did not accept the split completion transaction reset to 0 19 unexpected split completion rwc this bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode when this is set to 1, an unexpected split completion has been received with the requester id equaled to the primary bus number, device number, and function number at the pi7x9x110 primary bus interface reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 98 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 20 split completion overrun rwc when this bit is set to 1, a split completion has been terminated by pi7c9x110 with either a retry or disc onnect at the next adb due to the buffer full condition reset to 0 21 split request delayed rwc when this bit is set to 1, a split request is delayed because pi7c9x110 is not able to forward the split request tran saction to its primary bus due to insufficient room with in the limit specified in the split transaction commitment limit field of the downstream split transaction control register reset to 0 31:22 reserved ro 0000000000 7.5.58 upstream split transaction register ? offset 88h bit function type description 15:0 upstream split transaction capability ro upstream split transaction capability sp ecifies the size of the buffer (in the unit of adqs) to store split completions fo r memory read. it applies to the requesters on the secondary bus in addressing the completers on the primary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h 31:16 upstream split transaction commitment limit rw upstream split transaction commitment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x110 is allowed to forward all split requests of any size rega rdless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 7.5.59 downstream split transaction register ? offset 8ch bit function type description 15:0 downstream split transaction capability ro downstream split transaction capability specifies the size of the buffer (in the unit of adqs) to store split completions for memory read. it applies to the requesters on the primary bus in addressing the completers on the secondary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h 31:16 downstream split transaction commitment limit rw downstream split transaction comm itment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x110 is allowed to forward all split requests of any size rega rdless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 7.5.60 power management id register ? offset 90h bit function type description 7:0 power management id ro po wer management id register reset to 01h
pi7c9x110 pcie-to-pci reversible bridge page 99 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.61 next capability pointer register ? offset 90h bit function type description 15:8 next pointer ro next pointer (point to subsystem id and subsystem vendor id) reset to a8h 7.5.62 power management capability register ? offset 90h bit function type description 18:16 version number ro version number that complies with revision 2.0 of the pci power management interface specification. reset to 010 19 pme clock ro pme clock is not required for pme_l generation reset to 0 20 reserved ro reset to 0 21 device specific initialization (dsi) ro dsi ? no special initialization of th is function beyond the standard pci configuration header is required following transition to the d0 un-initialized state reset to 0 24:22 aux current ro 000: 0ma 001: 55ma 010: 100ma 011: 160ma 100: 220ma 101: 270ma 110: 320ma 111: 375ma reset to 001 25 d1 power management ro d1 pow er management is not supported reset to 0 26 d2 power management ro d2 pow er management is not supported reset to 0 31:27 pme_l support ro pme_l is supported in d3 cold, d3 hot, and d0 states. reset to 11001 7.5.63 power management control and status register ? offset 94h bit function type description 1:0 power state rw power state is used to determ ine the current power state of pi7c9x110. if a non-implemented state is written to th is register, pi7c9x110 will ignore the write data. when present state is d3 and changing to d0 state by programming this register, the power state change causes a device reset without activating the rese t_l of pci bus interface 00: d0 state 01: d1 state not implemented 10: d2 state not implemented 11: d3 state reset to 00 7:2 reserved ro reset to 000000
pi7c9x110 pcie-to-pci reversible bridge page 100 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 8 pme enable rws 0: pme_l assertion is disabled 1: pme_l assertion is enabled reset to 0 12:9 data select ro data re gister is not implemented reset to 0000 14:13 data scale ro data re gister is not implemented reset to 00 15 pme status rwcs pme_l is supported reset to 0 7.5.64 pci-to-pci support exten sion register ? offset 94h bit function type description 21:16 reserved ro reset to 000000 22 b2/b3 support ro 0: b2 / b3 not support for d3hot reset to 0 23 pci bus power/clock control enable ro 0: pci bus power/clock disabled reset to 0 31:24 data register ro data register is not implemented reset to 00h 7.5.65 downstream memory 0 translated base register ? offset 98h bit function type description 11:0 reserved ro reset to 000h 31:12 downstream memory 0 translated base rw define the translated base addre ss for downstream memory transactions whose initiator addresses fall into do wnstream memory 0 (above lower 4k boundary) address range. the number of b its that are used for translated base is determined by its setup register (offset 9ch) reset to 00000h 7.5.66 downstream memory 0 setup register ? offset 9ch bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 11:4 reserved ro reset to 00h 30:12 base address register size ro (ws) 0: set the corresponding bit in the base address register to read only. 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range. reset to 7ffffh
pi7c9x110 pcie-to-pci reversible bridge page 101 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31 base address register enable ro (ws) always set to 1 when a bus master atte mpts to write a zero to this bit. pi7c9x110 returns bit [31:12] as fffffh (for 4kb size). reset to 1 7.5.67 capability id register ? offset a0h bit function type description 7:0 capability id ro capability id fo r slot identification. si is o ff by default but can be turned on through eeprom interface reset to 04h
pi7c9x110 pcie-to-pci reversible bridge page 102 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.68 next pointer register ? offset a0h bit function type description 15:8 next pointer ro next pointer ? poi nts to pci express capabilities register reset to b0h 7.5.69 slot number register ? offset a0h bit function type description 20:16 expansion slot number rw expansion slot number reset to 00000 21 first in chassis rw first in chassis reset to 0 23:22 reserved ro reset to 00 7.5.70 chassis number register ? offset a0h bit function type description 31:24 chassis number rw chassis number reset to 00h 7.5.71 secondary clock and clkrun control register ? offset a4h bit function type description 1:0 s_clkout0 enable rw s_clkout (slot 0) enable for forward bridge mode only 00: enable s_clkout0 01: enable s_clkout0 10: enable s_clkout0 11: disable s_clkout0 and driven low reset to 00 3:2 s_clkout1 enable rw s_clkout (slot 1) enable for forward bridge mode only 00: enable s_clkout1 01: enable s_clkout1 10: enable s_clkout1 11: disable s_clkout1 and driven low reset to 00 5:4 s_clkout2 enable rw s_clkout (slot 2) enable for forward bridge mode only 00: enable s_clkout2 01: enable s_clkout2 10: enable s_clkout2 11: disable s_clkout2 and driven low reset to 00 7:6 s_clkout3 enable rw s_clkout (slot 3) enable for forward bridge mode only 00: enable s_clkout3 01: enable s_clkout3 10: enable s_clkout3 11: disable s_clkout3 and driven low reset to 00
pi7c9x110 pcie-to-pci reversible bridge page 103 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 8 s_clkout4 enable rw s_clkout (device 1) enable for forward bridge mode only 0: enable s_clkout4 1: disable s_clkout4 and driven low reset to 0 9 s_clkout5 enable rw s_clkout (device 2) enable for forward bridge mode only 0: enable s_clkout5 1: disable s_clkout5 and driven low reset to 0 10 s_clkout6 enable rw s_clkout (device 3) enable for forward bridge mode only 0: enable s_clkout6 1: disable s_clkout6 and driven low reset to 0 11 s_clkout7 enable rw s_clkout (device 4) enable for forward bridge mode only 0: enable s_clkout7 1: disable s_clkout7 and driven low reset to 0 12 s_clkout8 enable rw s_clkout (the bridge ) enable for forward bridge mode only 0: enable s_clkout8 1: disable s_clkout8 and driven low reset to 0 13 secondary clock stop status ro secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped reset to 0 14 secondary clkrun protocol enable rw 0: disable protocol 1: enable protocol reset to 0 15 clkrun mode rw 0: stop the secondary cl ock only when bridge is at d3hot state 1: stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus reset to 0 31:16 reserved ro reset to 0000h 7.5.72 donwstream i/o or memory 1 translated base register ? offset a8h bit function type description 5:0 reserved ro reset to 000000 31:6 downstream i/o or memory 1 translated base rw define the translated base address for downstream i/o or memory transactions whose initiator addresses fa ll into downstream i/o or memory 1 address range. the number of bits that are used for translated base is determined by its setup register (offset ach) reset to 00000h
pi7c9x110 pcie-to-pci reversible bridge page 104 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.73 dowstream i/o or memory 1 setup register ? offset ach bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 5:4 reserved ro reset to 00 30:6 base address register size ro (ws) 0: set the corresponding bit in the base address register to read only. 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range. if memory space is selected, bit [11:6] should be set to zeros. reset to 00000000h 31 base address register enable ro (ws) 0: disable this base address register 1: enable this base address register reset to 0 7.5.74 pci express capability id register ? offset b0h bit function type description 7:0 pci express capability id ro pci express capability id reset to 10h 7.5.75 next capability pointer register ? offset b0h bit function type description 15:8 next item pointer ro next ite m pointer (points to vpd register) reset to d8h 7.5.76 pci express capabilit y register ? offset b0h bit function type description 19:16 capability version ro reset to 1h 23:20 device / port type ro 0000: pci express endpoint device 0001: legacy pci express endpoint device 0100: root port of pci express root complex 0101: upstream port of pci express switch 0110: downstream port of pci express switch 0111: pci express to pci bridge 1000: pci to pci express bridge others: reserved reset to 7h for forward bridge or 8h for reverse bridge 24 slot implemented ro reset to 0 for fo rward bridge or 1 for reverse bridge 29:25 interrupt message nu mber ro reset to 0h 31:30 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 105 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.77 device capability register ? offset b4h bit function type description 2:0 maximum payload size ro 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 001 4:3 phantom functions ro no phantom functions supported reset to 00 5 8-bit tag field ro 8-bit tag field supported reset to 1 8:6 endpoint l0?s latency ro endpoint l0?s acceptable latency 000: less than 64 ns 001: 64 ? 128 ns 010: 128 ? 256 ns 011: 256 ? 512 ns 100: 512 ns ? 1 us 101: 1 ? 2 us 110: 2 ? 4 us 111: more than 4 us reset to 000 11:9 endpoint l1?s latency ro endpoint l1?s acceptable latency 000: less than 1 us 001: 1 ? 2 us 010: 2 ? 4 us 011: 4 ? 8 us 100: 8 ? 16 us 101: 16 ? 32 us 110: 32 ? 64 us 111: more than 64 us reset to 000 12 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 13 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 17:15 reserved ro reset to 000 25:18 captured slot power limit value ro these bits are set by the set_slot_power_limit message reset to 00h
pi7c9x110 pcie-to-pci reversible bridge page 106 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 27:26 captured slot power limit scale ro this value is set by the set_slot_power_limit message reset to 00 31:28 reserved ro reset to 0h 7.5.78 device control register ? offset b8h bit function type description 0 correctable error reporting enable rw reset to 0h 1 non-fatal error reporting enable rw reset to 0h 2 fatal error reporting enable rw reset to 0h 3 unsupported request reporting enable rw reset to 0h 4 relaxed ordering enable ro relaxed ordering disabled reset to 0h 7:5 max payload size rw this field sets the maximum tlp payload size for the pi7c9x110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 000 8 extended tag field enable rw reset to 0 9 phantom functions enable ro phantom functions not supported reset to 0 10 auxiliary power pm enable ro auxiliary power pm not supported reset to 0 11 no snoop enable ro bridge never sets the no snoop attribute in the transaction it initiates reset to 0 14:12 maximum read request size rw this field sets the maximum read request size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 2h 15 configuration retry enable rw reset to 0 7.5.79 device status register ? offset b8h bit function type description 16 correctable error detected rwc reset to 0 17 non-fatal error detected rwc reset to 0 18 fatal error detected rwc reset to 0 19 unsupported request detected rwc reset to 0 20 aux power detected ro reset to 1
pi7c9x110 pcie-to-pci reversible bridge page 107 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 21 transaction pending ro 0: no transaction is pending on transaction layer interface 1: transaction is pending on transaction layer interface reset to 0 31:22 reserved ro reset to 0000000000 7.5.80 link capability register ? offset bch bit function type description 3:0 maximum link speed ro indicates th e maximum speed of the express link 0001: 2.5gb/s link reset to 1 9:4 maximum link width ro indicates the maximu m width of the express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 11:10 aspm support ro this field indicates the level of active state power management support 00: reserved 01: l0?s entry supported 10: reserved 11: l0?s and l1?s supported reset to 11 14:12 l0?s exit latency ro reset to 3h 17:15 l1?s exit latency ro reset to 0h 23:18 reserved ro reset to 0h 31:24 port number ro reset to 00h 7.5.81 link control register ? offset c0h bit function type description 1:0 aspm control rw this field controls th e level of aspm supported on the express link 00: disabled 01: l0?s entry enabled 10: l1?s entry enabled 11: l0?s and l1?s entry enabled reset to 00 2 reserved ro reset to 0 3 read completion boundary (rcb) ro read completion boundary not supported reset to 0 4 link disable ro / rw ro for forward bridge reset to 0 5 retrain link ro / rw ro for forward bridge reset to 0 6 common clock configuration rw reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 108 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 7 extended sync rw reset to 0 15:8 reserved ro reset to 00h
pi7c9x110 pcie-to-pci reversible bridge page 109 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.82 link status register ? offset c0h bit function type description 19:16 link speed ro this field indicates the negotiated speed of the express link 001: 2.5gb/s link reset to 1h 25:20 negotiated link width ro 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 26 link train error ro reset to 0 27 link training ro reset to 0 28 slot clock configuration ro reset to 1 31:29 reserved ro reset to 0 7.5.83 slot capability register ? offset c4h bit function type description 0 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 1 power controller present ro reset to 0 2 mrl sensor present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 3 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 4 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 5 hot plug surprise ro reset to 0 6 hot plug capable ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14:7 slot power limit value ro reset to 00h 16:15 slot power limit scale ro reset to 00 18:17 reserved ro reset to 00 31:19 physical slot number ro reset to 0 7.5.84 slot control register ? offset c8h bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 110 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 0 attention button present enable rw reset to 0 1 power fault detected enable rw reset to 0 2 mrl sensor changed enable rw reset to 0 3 presence detect changed enable rw reset to 0 4 command completed interrupt enable rw reset to 0 5 hot plug interrupt enable rw reset to 0 7:6 attention indicator control rw reset to 0 9:8 power indicator control rw reset to 0 10 power controller control rw reset to 0 15:11 reserved ro reset to 0 7.5.85 slot status register ? offset c8h bit function type description 16 attention button pressed ro reset to 0 17 power fault detected ro reset to 0 18 mrl sensor changed ro reset to 0 19 presence detect changed ro reset to 0 20 command completed ro reset to 0 21 mrl sensor state ro reset to 0 22 presence detect state ro reset to 0 31:23 reserved ro reset to 0 7.5.86 xpip configuration register 0 ? offset cch bit function type description 0 hot reset enable rw reset to 0 1 loopback function enable rw reset to 0 2 cross link function enable rw reset to 0 3 software direct to configuration state when in ltssm state rw reset to 0 4 internal selection for debug mode rw reset to 0 7:5 negotiate lane number of times rw reset to 3h 12:8 ts1 number counter rw reset to 10h 15:13 reserved ro reset to 0 31:16 ltssm enter l1 timer default value rw reset to 0400h 7.5.87 xpip configuration register 1 ? offset d0h bit function type description 9:0 l0?s lifetime timer rw reset to 0 15:10 reserved ro reset to 0 31:16 l1 lifetime timer rw reset to 0 7.5.88 xpip configuration register 2 ? offset d4h bit function type description 7:0 cdr recovery time (in the number of fts order sets) rw reset to 54h a fast training sequence order set co mposes of one k28.5 (com) symbol and three k28.1 symbols. 14:8 l0?s exit to l0 latency rw reset to 2h
pi7c9x110 pcie-to-pci reversible bridge page 111 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 15 reserved ro reset to 0 22:16 l1 exit to l0 latency rw reset to 19h 31:23 reserved ro reset to 0 7.5.89 capability id register ? offset d8h bit function type description 7:0 capability id for vpd register ro reset to 03h 7.5.90 next pointer register ? offset d8h bit function type description 15:8 next pointer ro next pointer (f0h, points to msi capabilities) reset to f0h 7.5.91 vpd register ? offset d8h bit function type description 17:16 reserved ro reset to 0 23:18 vpd address for read/write cycle rw reset to 0 30:24 reserved ro reset to 0 31 vpd operation rw 0: generate a read cycle fr om the eeprom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?0? until eeprom cycle is finished, after which the bit is then set to ?1?. data for reads is available at register ech. 1: generate a write cycle to the eep rom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?1? until eeprom cycle is finished, after which it is then cleared to ?0?. reset to 0 7.5.92 vpd data register ? offset dch bit function type description 31:0 vpd data rw vpd data (eeprom data [address + 0x40]) the least significant byte of this regist er corresponds to the byte of vpd at the address specified by the vpd addre ss register. the data read form or written to this register uses the normal pci byte tr ansfer capabilities. reset to 0 7.5.93 upstream memory 0 translated base register ? offset e0h bit function type description 11:0 reserved ro reset to 000h 31:12 downstream memory 0 translated base rw define the translated base address for upstream memory transactions whose initiator addresses fall into upstream memory 0 (above lower 4k boundary) address range. the number of bits th at are used for translated base is determined by its setup register (offset e4h) reset to 00000h
pi7c9x110 pcie-to-pci reversible bridge page 112 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.94 upstream memory 0 s etup register ? offset e4h bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 11:4 reserved ro reset to 00h 30:12 base address register size ro (ws) 0: set the corresponding bit in the base address register to read only. 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range. reset to 00000h 31 base address register enable ro (ws) always set to 1 when a bus master atte mpts to write a zero to this bit. pi7c9x110 returns bit [31:12] as fffffh (for 4kb size). reset to 1 7.5.95 upstream i/o or memory 1 t ranslated base register ? offset e8h bit function type description 5:0 reserved ro reset to 000000 31:6 upstream i/o or memory 1 translated base rw define the translated base address for upstream i/o or memory transactions whose initiator addresses fall into upst ream i/o or memory 1 address range. the number of bits that are used for tran slated base is determined by its setup register (offset ech) reset to 00000h 7.5.96 upstream i/o or memory 1 setup register ? offset ech bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 5:4 reserved ro reset to 00 30:6 base address register size ro (ws) 0: set the corresponding bit in the base address register to read only. 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range. if memory space is selected, bit [11:6] should be set to zeros. reset to 00000000h
pi7c9x110 pcie-to-pci reversible bridge page 113 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31 base address register enable ro (ws) 0: disable this base address register 1: enable this base address register reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 114 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.97 message signaled interrupts id register ? f0h bit function type description 7:0 capability id for msi registers ro reset to 05h 7.5.98 next capabilities pointer register ? f0h bit function type description 15:8 next pointer ro next pointer (00h indicates the end of capabilities) reset to 00h 7.5.99 message control register ? offset f0h bit function type description 16 msi enable rw 0: disable msi and default to intx for interrupt 1: enable msi for interrupt service and ignore intx interrupt pins 19:17 multiple message capable ro 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 22:20 multiple message enable rw 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 23 64-bit address capable rw reset to 1 31:24 reserved ro reset to 00h 7.5.100 message address register ? offset f4h bit function type description 1:0 reserved ro reset to 00 31:2 system specified message address rw reset to 0 7.5.101 message upper address register ? offset f8h bit function type description 31:0 system specified message upper address rw reset to 0 7.5.102 message data register ? offset fch bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 115 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 15:0 system specified message data rw reset to 0 31:16 reserved ro reset to 0 7.5.103 advance error re porting capability id register ? offset 100h bit function type description 15:0 advance error reporting capability id ro reset to 0001h 7.5.104 advance error repo rting capability version register ? offset 100h bit function type description 19:16 advance error reporting capability version ro reset to 1h 7.5.105 next capability o ffset register ? offset 100h bit function type description 31:20 next capability offset ro next cap ability offset (150h poi nts to vc capability) reset to 150h 7.5.106 uncorrectable error status register ? offset 104h bit function type description 0 training error status rwcs reset to 0 3:1 reserved ro reset to 0 4 data link protocol error status rwcs reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp status rwcs reset to 0 13 flow control protocol error status rwcs reset to 0 14 completion timeout status rwcs reset to 0 15 completer abort status rwcs reset to 0 16 unexpected completion status rwcs reset to 0 17 receiver overflow status rwcs reset to 0 18 malformed tlp status rwcs reset to 0 19 ecrc error status rwcs reset to 0 20 unsupported request error status rwcs reset to 0 31:21 reserved ro reset to 0 7.5.107 uncorrectab le error mask register ? offset 108h bit function type description 0 training error mast rws reset to 0 3:1 reserved ro reset to 0 4 data link protocol error mask rws reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp mask rws reset to 0 13 flow control protocol error mask rws reset to 0 14 completion timeout mask rws reset to 0 15 completion abort mask rws reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 116 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 16 unexpected completion mask rws reset to 0 17 receiver overflow mask rws reset to 0 18 malformed tlp mask rws reset to 0 19 ecrc error mask rws reset to 0 20 unsupported request error mask rws reset to 0 31:21 reserved ro reset to 0 7.5.108 uncorrectable error severity register ? offset 10ch bit function type description 0 training error severity rws reset to 1 3:1 reserved ro reset to 0 4 data link protocol error severity rws reset to 1 11:5 reserved ro reset to 0 12 poisoned tlp severity rws reset to 0 13 flow control protocol error severity rws reset to 1 14 completion timeout severity rws reset to 0 15 completer abort seve rity rws reset to 0 16 unexpected completion severity rws reset to 0 17 receiver overflow severity rws reset to 1 18 malformed tlp severity rws reset to 1 19 ecrc error severity rws reset to 0 20 unsupported request error severity rws reset to 0 31:21 reserved ro reset to 0 7.5.109 correctable error stat us register ? offset 110h bit function type description 0 receiver error status rwcs reset to 0 5:1 reserved ro reset to 0 6 bad tlp status rwcs reset to 0 7 bad dllp status rwcs reset to 0 8 replay_num rollover status rwcs reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout status rwcs reset to 0 31:13 reserved ro reset to 0 7.5.110 correctable error ma sk register ? offset 114h bit function type description 0 receiver error mask rws reset to 0 5:1 reserved ro reset to 0 6 bad tlp mask rws reset to 0 7 bad dllp mask rws reset to 0 8 replay_num rollover mask rws reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout mask rws reset to 0 31:13 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 117 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.5.111 advanced error capabilities and control register ? offset 118h bit function type description 4:0 first error pointer ros reset to 0h 5 ecrc generation capable ro reset to 1 6 ecrc generation enable rws reset to 0 7 ecrc check capable ro reset to 1 8 ecrc check enable rws reset to 0 31:9 reserved ro reset to 0 7.5.112 header log register 1 ? offset 11ch bit function type description 7:0 header byte 3 ros reset to 0 15:8 header byte 2 ros reset to 0 23:16 header byte 1 ros reset to 0 31:24 header byte 0 ros reset to 0 7.5.113 header log register 2 ? offset 120h bit function type description 7:0 header byte 7 ros reset to 0 15:8 header byte 6 ros reset to 0 23:16 header byte 5 ros reset to 0 31:24 header byte 4 ros reset to 0 7.5.114 header log register 3 ? offset 124h bit function type description 7:0 header byte 11 ros reset to 0 15:8 header byte 10 ros reset to 0 23:16 header byte 9 ros reset to 0 31:24 header byte 8 ros reset to 0 7.5.115 header log register 4 ? offset 128h bit function type description 7:0 header byte 15 ros reset to 0 15:8 header byte 14 ros reset to 0 23:16 header byte 13 ros reset to 0 31:24 header byte 12 ros reset to 0 7.5.116 secondary uncorrectable error status register ? offset 12ch bit function type description 0 target abort on split completion status rwcs reset to 0 1 master abort on split completion status rwcs reset to 0 2 received target abort status rwcs reset to 0 3 received master abort status rwcs reset to 0 4 reserved ro reset to 0 5 unexpected split completion error status rwcs reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 118 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 6 uncorrectable split completion message data error status rwcs reset to 0 7 uncorrectable data error status rwcs reset to 0 8 uncorrectable attribute error status rwcs reset to 0 9 uncorrectable address error status rwcs reset to 0 10 delayed transaction discard timer expired status rwcs reset to 0 11 perr_l assertion detected status rwcs reset to 0 12 serr_l assertion detected status rwcs reset to 0 13 internal bridge error status rwcs reset to 0 31:14 reserved ro reset to 0 7.5.117 secondary uncorrectable e rror mask register ? offset 130h bit function type description 0 target abort on split completion mask rws reset to 0 1 master abort on split completion mask rws reset to 0 2 received target abort mask rws reset to 0 3 received master abort mask rws reset to 1 4 reserved ro reset to 0 5 unexpected split completion error mask rws reset to 1 6 uncorrectable split completion message data error mask rws reset to 0 7 uncorrectable data error mask rws reset to 1 8 uncorrectable attribute error mask rws reset to 1 9 uncorrectable address error mask rws reset to 1 10 delayed transaction discard timer expired mask rws reset to 1 11 perr_l assertion detected mask rws reset to 0 12 serr_l assertion detected mask rws reset to 1 13 internal bridge error mask rws reset to 0 31:14 reserved ro reset to 0 7.5.118 secondary uncorrectable erro r severity register ? offset 134h bit function type description 0 target abort on split completion severity rws reset to 0 1 master abort on split completion severity rws reset to 0 2 received target abort severity rws reset to 0 3 received master abort severity rws reset to 0 4 reserved ro reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 119 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 5 unexpected split completion error severity rws reset to 0 6 uncorrectable split completion message data error severity rws reset to 1 7 uncorrectable data error severity rws reset to 0 8 uncorrectable attribute error severity rws reset to 1 9 uncorrectable address error severity rws reset to 1 10 delayed transaction discard timer expired severity rws reset to 0 11 perr_l assertion detected severity rws reset to 0 12 serr_l assertion detected severity rws reset to 1 13 internal bridge error severity rws reset to 0 31:14 reserved ro reset to 0 7.5.119 secondary error capability and control register ? offset 138h bit function type description 4:0 secondary first error pointer row reset to 0 31:5 reserved ro reset to 0 7.5.120 secondary header log re gister ? offset 13ch ? 148h bit function type description 35:0 transaction attribute ros tran saction attribute, cbe [3:0] and ad [31:0] during attribute phase reset to 0 39:36 transaction command lower ros transaction command lower, cbe [3:0] during first address phase reset to 0 43:40 transaction command upper ros transaction command upper, cbe [3 :0] during second address phase of dac transaction reset to 0 63:44 reserved ros reset to 0 95:64 transaction address ros transaction addr ess, ad [31:0] during first address phase reset to 0 127:96 transaction address ros transaction addres s, ad [31:0] during second address phase of dac transaction reset to 0 7.5.121 reserved register ? offset 14ch 7.5.122 vc capability id register ? offset 150h bit function type description 15:0 vc capability id ro reset to 0002h 7.5.123 vc capability version register ? offset 150h
pi7c9x110 pcie-to-pci reversible bridge page 120 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 19:16 vc capability version ro reset to 1h 7.5.124 next capability o ffset register ? offset 150h bit function type description 31:20 next capability offset ro next capability offset ? th e end of capabilities reset to 0 7.5.125 port vc capability register 1 ? offset 154h bit function type description 2:0 extended vc count ro reset to 0 3 reserved ro reset to 0 6:4 low priority extended vc count ro reset to 0 7 reserved ro reset to 0 9:8 reference clock ro reset to 0 11:10 port arbitration table entry size ro reset to 0 31:12 reserved ro reset to 0 7.5.126 port vc capability register 2 ? offset 158h bit function type description 7:0 vc arbitration capability ro reset to 0 23:8 reserved ro reset to 0 31:24 vc arbitration table offset ro reset to 0 7.5.127 port vc control register ? offset 15ch bit function type description 0 load vc arbitration table ro reset to 0 3:1 vc arbitration select ro reset to 0 15:4 reserved ro reset to 0 7.5.128 port vc status register ? offset 15ch bit function type description 16 vc arbitration table status ro reset to 0 31:17 reserved ro reset to 0 7.5.129 vc0 resource capability register ? offset 160h bit function type description 7:0 port arbitration capability ro reset to 0 13:8 reserved ro reset to 0 14 advanced packet switching ro reset to 0 15 reject snoop transactions ro reset to0 22:16 maximum time slots ro reset to 0 23 reserved ro reset to 0 31:24 port arbitration table offset ro reset to 0 7.5.130 vc0 resource control register ? offset 164h bit function type description
pi7c9x110 pcie-to-pci reversible bridge page 121 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 0 tc / vc map ro for tc0 reset to 1 7:1 tc / vc map rw for tc7 to tc1 reset to 7fh 15:8 reserved ro reset to 0 16 load port arbitration table ro reset to 0 19:17 port arbitration select ro reset to 0 23:20 reserved ro reset to 0 26:24 vc id ro reset to 0 30:27 reserved ro reset to 0 31 vc enable ro reset to 1 7.5.131 vc0 resource status register ? offset 168h bit function type description 0 port arbitration table 1 ro reset to 0 1 vc0 negotiation pending ro reset to 0 31:2 reserved ro reset to 0 7.5.132 reserved registers ? offset 16ch ? 300h 7.5.133 extra gpi/gpo data and control register ? offset 304h bit function type description 3:0 extra gpo rwc gpo [3:0], write 1 to clear reset to 0 7:4 extra gpo rws gpo [3:0], write 1 to set reset to 0 11:8 extra gpo enable rwc gpo [3 :0] enable, write 1 to clear reset to 0 15:12 extra gpo enable rws gpo [3:0] enable, write 1 to set reset to 0 19:16 extra gpi ro extra gpi [3:0] data register reset to 0 31:20 reserved ro reset to 0 7.5.134 reserved registers ? offset 308h ? 30ch 7.5.135 replay and acknowledge latency timers ? offset 310h bit function type description 11:0 replay timer rw replay timer reset to 0 12 replay timer enable rw replay timer enable reset to 0 15:13 reserved ro reset to 0 29:16 acknowledge latency timer rw acknowledge latency timer reset to 0 30 acknowledge latency timer enable ro acknowledge latency timer enable reset to 0 31 reserved ro reset to 0 7.5.136 reserved registers ? offset 314h ? ffch
pi7c9x110 pcie-to-pci reversible bridge page 122 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6 control and status register s for non-transparent bridge mode control and status registers (csr?s ) can be accessed by memory or i/o transactions from both primary and secondary ports. the csr?s are defined and to be used along with configuration registers (see previous section 7.5 for details) for non-transparent bridge operations. register type descriptions ro read only ros read only and sticky rw read/write rwc read/write ?1? to clear rws read/write and sticky rwcs read/write ?1? to clear and sticky 7.6.1 reserved registers ? offset 000h to 004h 7.6.2 downstream memory 2 translat ed base register ? offset 008h bit function type description 11:0 reserved ro reset to 000h 31:12 downstream memory 2 translated base rw define the translated base addre ss for downstream memory transactions whose initiator addresses fall into down stream memory 2 address range. the number of bits that are used for transl ated base is determined by its setup register (offset 00ch) reset to 00000h 7.6.3 downstream memory 2 setup register ? offset 00ch bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 11:4 reserved ro reset to 00 30:12 base address register size ro (ws) 0: set the corresponding bit in the ba se address register to read only 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range reset to 00000h 31 base address register enable ro (ws) 0: disable this base address register 1: enable this base address register reset to 0 7.6.4 downstream memory 3 translat ed base register ? offset 010h bit function type description 11:0 reserved ro reset to 000000
pi7c9x110 pcie-to-pci reversible bridge page 123 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 31:12 downstream memory 3 translated base rw define the translated base addre ss for downstream memory transactions whose initiator addresses fall into down stream memory 3 address range. the number of bits that are used for transl ated base is determined by its setup register (offset 014h) reset to 00000h 7.6.5 downstream memory 3 se tup register ? offset 014h bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro (ws) 00: 32-bit address space 01: 64-bit address space reset to 00 3 prefetchable control ro (ws) 0: non-prefetchable 1: prefetchable reset to 0 11:4 reserved ro reset to 00 30:12 base address register size ro (ws) 0: set the corresponding bit in the ba se address register to read only 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range reset to 00000h 31 base address register enable ro (ws) 0: disable this base address register 1: enable this base address register reset to 0 7.6.6 downstream memory 3 upper 32- bit setup register ? offset 018h bit function type description 30:0 base address register size rw 0: set the correspondi ng bit in the upper 32-bit base address register to read only 1: set the corresponding bit in the upper 32-bit base address register to read/write in order to contro l the size of the address range reset to 00000000h 31 base address register enable rw) 0: disable 64-bit base address register 1: enable 64-bit base address register reset to 0 7.6.7 reserved registers ? offset 01ch to 030h 7.6.8 upstream memory 3 s etup register ? offset 34h bit function type description 0 type selector ro 0: memory space is requested reset to 0 2:1 address type ro 00: 32-bit address space 01: 64-bit address space reset to 01
pi7c9x110 pcie-to-pci reversible bridge page 124 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 3 prefetchable control rw 0: non-prefetchable 1: prefetchable reset to 0 11:4 reserved ro reset to 00 31:12 base address register size rw 0: set the corres ponding bit in the base address register to read only 1: set the corresponding bit in the base address register to read/write in order to control the size of the address range reset to 00000h 7.6.9 upstream memory 3 upper 32- bit setup register ? offset 038h bit function type description 30:0 base address register size rw 0: set the correspondi ng bit in the upper 32-bit base address register to read only 1: set the corresponding bit in the upper 32-bit base address register to read/write in order to contro l the size of the address range reset to 00000000h 31 base address register enable rw 0: disable 64-bit base address register 1: enable 64-bit base address register reset to 0 7.6.10 reserved registers ? offset 03ch to 04ch 7.6.11 lookup table offset ? offset 050h bit function type description 7:0 lookup table offset rw this register contains the byte offset of the lookup table entry to be accessed for upstream memory 2. the access is initiated when the lookup table data register is accessed. this register should be written first before any lookup table data access. reset to 00h 31:8 reserved ro reset to 0 7.6.12 lookup table data ? offset 054h bit function type description 0 valid rw 0: invalid lookup 1: valid lookup reset to 0 2:1 reserved ro reset to 00 3 prefetchable rw 0: memory address is non-prefetchable 1: memory address is reset to 0 7:4 reserved ro reset to 0h
pi7c9x110 pcie-to-pci reversible bridge page 125 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 bit function type description 24:8 translated base or reserved rw/ro data written or re ad from the lookup table at the offset specified in the lookup table offset register . when writing to this register, the data value is written to the specified lookup table entry. when reading from this register, the data reflects the data value from the specified lookup table entry. the bit [24:8] is translated base register bit when the lookup table size is set to 256b range. the bit [24:8] is reserved when the lookup table size is set to 32mb range (see pci configuration offset 68h for non- transparent mode). reset to 0 31:25 translated base rw data written or read from the lookup table at the offset specified in the lookup table offset register . when writing to this register, the data value is written to a specific lookup table en try (csr offset 100h ? 1ffh). when reading from this register, the data re flects the data value from the specific lookup table entry. reset to 0 7.6.13 upstream page boundary irq 0 request register ? offset 058h bit function type description 31:0 upstream page boundary irq 0 rwc each interrupt request bit is correspondent to a page entry in the lower half of the upstream memory 2 range. bit [0] is for the first page, and bit [31] is for the 32 nd page. pi7c9x110 sets the appr opriate bit when it successfully transfers data to or from the imitator th at addresses the last double word in a page. pi7c9x110 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding upstream page boundary irq 0 mask bit is reset. when forward bridge, pi7c9x110 asserts inta_l or generates msi on secondary bus (pci interface). when reverse bridge, pi7c9x110 sends inta_l asse rtion message or generates msi on secondary interface (pci express). when writing a ?1? to this register, it clears the corresponding interrupt request bit. reset to 0 7.6.14 upstream page boundary irq 1 request register ? offset 05ch bit function type description 31:0 upstream page boundary irq 1 rwc each interrupt request bit is correspondent to a page entry in the lower half of the upstream memory 2 range. bit [0] is for the 33 rd page, and bit [31] is for the 64 th page. pi7c9x110 sets the appr opriate bit when it successfully transfers data to or from the initiator that addresses the last double word in a page. pi7c9x110 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding upstream page boundary irq 1 mask bit is reset. when forward bridge, pi7c9x110 asserts inta_l or generates msi on secondary bus (pci interface). when reverse bridge, pi7c9x110 sends inta_l asse rtion message or generates msi on secondary interface (pci express). when wrting a ?1? to this register, it clears the corresponding interrupt request bit. reset to 0
pi7c9x110 pcie-to-pci reversible bridge page 126 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.15 upstream page boundary ir q 0 mask register ? offset 060h bit function type description 31:0 upstream page boundary irq 0 mask rwc 0: pi7c9x110 can initiate an inte rrupt request when the correspondent request bit is set 1: pi7c9x110 cannot initiate any interrupt request even though the correspondent request bit is set reset to ffffffffh 7.6.16 upstream page boundary ir q 1 mask register ? offset 064h bit function type description 31:0 upstream page boundary irq 1 mask rwc 0: pi7c9x110 can initiate an inte rrupt request when the correspondent request bit is set 1: pi7c9x110 cannot initiate any interrupt request even though the correspondent request bit is set reset to ffffffffh 7.6.17 reserved register ? offset 068c 7.6.18 primary clear irq register ? offset 070h bit function type description 15:0 primary clear irq rwc when writing ?1? to this register bit, it clears the correspondent interrupt request bit. when reading this register, it retu rns the interrupt request bit status: 0: it is not the bit that causes the interrupt request on primary interface 1: it is the bit that causes the interrupt request on primary interface reset to 0000h 7.6.19 secondary clear irq register ? offset 070h bit function type description 31:16 secondary clear irq rwc when writing ?1? to this register bit, it clears the correspondent interrupt request bit. when reading this register, it retu rns the interrupt request bit status: 0: it is not the bit that causes the interrupt request on secondary interface 1: it is the bit that causes the in terrupt request on secondary interface reset to 0000h
pi7c9x110 pcie-to-pci reversible bridge page 127 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.20 primary set irq register ? offset 074h bit function type description 15:0 primary set irq rws when writing ?1? to this regi ster bit, it set the correspondent interrupt request bit. when reading this register, it retu rns the interrupt request bit status: 0: it is not the bit that causes the interrupt request on primary interface 1: it is the bit that causes the interrupt request on primary interface reset to 0000h 7.6.21 secondary set irq register ? offset 074h bit function type description 31:16 secondary set irq rws when writing ?1? to this re gister bit, it set the corr espondent interrupt request bit. when reading this register, it retu rns the interrupt request bit status: 0: it is not the bit that causes the interrupt request on secondary interface 1: it is the bit that causes the in terrupt request on secondary interface reset to 0000h 7.6.22 primary clear irq mask register ? offset 078h bit function type description 15:0 primary clear irq mask rws when writing ?1? to th is register bit, it clears the correspondent interrupt request mask bit. when reading this register, it returns the primary clear irq mask bit status: 0: it allows to clear an interrupt request on primary interface 1: it does not allow to clear any interrupt request on primary interface reset to ffffh 7.6.23 secondary clear irq mask register ? offset 078h bit function type description 31:16 secondary clear irq mask rws when writing ?1? to th is register bit, it clears the correspondent interrupt request mask bit. when reading this register, it returns the secondary clear irq mask bit status: 0: it allows to clear an interrupt request on secondary interface 1: it does not allow to clear any interrupt request on secondary interface reset to ffffh
pi7c9x110 pcie-to-pci reversible bridge page 128 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.24 primary set irq mask register ? offset 07ch bit function type description 15:0 primary set irq mask rws when writing ?1? to this register bit, it set the correspondent interrupt request mask bit. when reading this register, it return s the primary set irq mask bit status: 0: it allows to set an interr upt request on primary interface 1: it does not allow to set any interrupt request on primary interface reset to ffffh 7.6.25 secondary set irq mask register ? offset 07ch bit function type description 31:16 secondary set irq mask rwc when writing ?1? to this register bit, it set the co rrespondent interrupt request mask bit. when reading this register, it returns the secondary set irq mask bit status: 0: it allows to set an interrupt request on secondary interface 1: it does not allow to set any in terrupt request on secondary interface reset to ffffh 7.6.26 reserved registers ? offset 080h to 09ch 7.6.27 scratchpad 0 register ? offset 0a0h bit function type description 31:0 scratchpad 0 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.28 scratchpad 1 register ? offset 0a4h bit function type description 31:0 scratchpad 1 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h
pi7c9x110 pcie-to-pci reversible bridge page 129 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.29 scratchpad 2 register ? offset 0a8h bit function type description 31:0 scratchpad 2 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.30 scratchpad 3 register ? offset 0ach bit function type description 31:0 scratchpad 3 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.31 scratchpad 4 register ? offset 0b0h bit function type description 31:0 scratchpad 4 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.32 scratchpad 5 register ? offset 0b4h bit function type description 31:0 scratchpad 5 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.33 scratchpad 6 register ? offset 0b8h bit function type description 31:0 scratchpad 6 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h
pi7c9x110 pcie-to-pci reversible bridge page 130 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 7.6.34 scratchpad 7 register ? offset 0bch bit function type description 31:0 scratchpad 7 rw the scratchpad is a 32-bit inte rnal register that can be accessed from both primary and secondary interfaces. the external devices can use the scratchpad as a temporary storage. primary and secondary bus devices can communicate through the scratchpad. however, writing and reading the scratchpad does not generate any interrupt request. reset to 00000000h 7.6.35 reserved registers ? offset 0c0h to 0fch 7.6.36 lookup table registers ? offset 100h to 1fch bit function type description 2047:0 lookup table rw the lookup table has 64 entries. each entry has 32-bit mapped to each page of the upstream memory 2 base address range 64 th page: bit [2047:2016] 63 rd page: bit [2015:1984] 62 nd page: bit [1983:1952] 61 st page: bit [1951:1920] 60 th page: bit [1919:1888] 59 th page: bit [1887:1856] 58 th page: bit [1855:1824] 57 th page: bit [1823:1792] 56 th page: bit [1791:1760] 55 th page: bit [1759:1728] 54 th page: bit [1727:1696] 53 rd page: bit [1695:1664] 52 nd page: bit [1663:1632] 51 st page: bit [1631:1600] 50 th page: bit [1599:1568] 49 th page: bit [1567:1536] 48 th page: bit [1535:1504] 47 th page: bit [1503:1472] 46 th page: bit [1471:1440] 45 th page: bit [1439:1408] 44 th page: bit [1407:1376] 43 rd page: bit [1375:1344] 42 nd page: bit [1343:1312] 41 st page: bit [1311:1280] 40 th page: bit [1279:1248] 39 th page: bit [1247:1216] 38 th page: bit [1215:1184] 37 th page: bit [1183:1152] 36 th page: bit [1151:1120] 35 th page: bit [1119:1088] 34 th page: bit [1087:1056] 33 rd page: bit [1055:1024] 32 nd page: bit [1023:992] 31 st page: bit [991:960] 30 th page: bit [959:928] 29 th page: bit [927:896] 28 th page: bit [895:864] 27 th page: bit [863:832] 26 th page: bit [831:800] 25 th page: bit [799:768] 24 th page: bit [767:736] 23 rd page: bit [735:704] 22 nd page: bit [703:672] 21 st page: bit [671:640] 20 th page: bit [639:608] 19 th page: bit [607:576] 18 th page: bit [575:544] 17 th page: bit [543:512] 16 th page: bit [511:480] 15 th page: bit [479:448] 14 th page: bit [447:416] 13 th page: bit [415:383] 12 th page: bit [382:352] 11 th page: bit [351:320] 10 th page: bit [319:288] 9 th page: bit [287:256] 8 th page: bit [255:224] 7 th page: bit [223:192] 6 th page: bit [191:160] 5 th page: bit [159:128] 4 th page: bit [127:96] 3 rd page: bit [95:64] 2 nd page: bit [63:32] 1 st page: bit [31:0] reset to unknown 7.6.37 reserved registers ? offset 200h to ffch
pi7c9x110 pcie-to-pci reversible bridge page 131 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 8 gpio pins and sm bus address gpio [3:1] of pi7c9x110 are defined for hot-plug usage if msk_in=1 during reset. please see configuration register definition (offset 78h ? 7bh). in forward bridge: gpio[0] : pci slot card presence detection input gpio[1] : attention button pressed input gpio[2] : power indication output gpio[3] : attention indication output in reverse bridge: gpio[0] : pcie slot ca rd presence detection input gpio[1] : mrl sensor input gpio[2] : reserved gpio[3] : reserved gpio [3:0] are also defined the address bits of smbus device id if sm bus is selected (tm1=1). the address- strapping table of smbus with gpio [3:0] pins is defined in the following table: table 8-1 sm bus device id strapping sm bus address bit sm bus device id address bit [7] = 1 address bit [6] = 1 address bit [5] = 0 address bit [4] = gpio [3] address bit [3] = gpio [2] address bit [2] = gpio [1] address bit [1] = gpio [0] gpio [3:0] pins can be further defined to serve other functions in the next generation device. four gpi [3:0] and four gpo [3:0] have been added to pi7c9x110 when external arbiter is selected (cfn_l=1). if external arbiter is selected, req_l [5:2] and gnt [5:2] will become the gpi [3:0] and gpo [3:0] respectively. if hot plug control is implemented thru pi7c9x110 device, the pin function of gpio [3:0] configured in forward or reverse mode are defined as follow: in forward mode: gpio[0] : pci slot card presence detection input gpio[1] : attenti on button pressed input gpio[2] : power indication output gpio[3] : attention indication output in reverse mode: gpio[0] : pcie slot card presence detection input gpio[1] : mrl sensor input gpio[2] : reserved gpio[3] : reserved
pi7c9x110 pcie-to-pci reversible bridge page 132 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 9 clock scheme pci express interface: pi7c9x110 requires 100mhz differential clock inputs through refclkp and refclkn pins. pci interface: pi7c9x110 requires pci clock (up to 66mhz and at least 10mhz) to be connected to the clkin. pi7c9x110 uses the clkin and generates nine clock outputs, clkout [8:0]. also, pi7c9x110 requires one of the clkout [8:0] (preferably clkout [8]) to be connected to fbclkin for the pci interface logic of pi7c9x110. the actual number of masters supported will vary depending on the loading of the pci bus. typically, pi7c9x110 can support up to four 66mhz pci slots or eight 33mhz pci slots. the pi7c9x110 pci clock outputs, clkout [8:0], can be enabled or disabled through the configuration register. 10 interrupts pi7c9x110 supports interrupt message packets on pcie side. pi7c9x110 supports pci interrupt (inta, b, c, d) pins or msi (message signaled interrupts) on pci side. pc i interrupts and msi are mutually exclusive. in order words, if msi is enabled, pci interrupts will be di sabled. pi7c9x110 support 64-bit addressing msi. in reverse bridge mode, pi7c9x110 maps the interrupt me ssage packets to pci interrupt pins or msi if msi is enable (see configuration regist er bit [16] of offset f0h). in forward bridge mode, pi7c9x110 maps the pci interrupts pins or msi if enable on pci side to interrupt message packets on pcie side. there are eight interrupt me ssage packets. they are assert_inta, assert_intb, assert_intc, assert_intd, deassert_inta, deassert_intb, deassert_intc, and dea ssert_intd. these eight interrupt messages are mapped to the four pci interrupts (inta, intb, intc, and intd). see table 10-1 for interrupt mapping information in reverse bridge mode. pi7c9x110 tracks the pci interrupt (inta, intb, intc, and intd) pins and maps them to the eight interrupt messages. see table 10-2 for in terrupt mapping information in forward bridge mode. table 10-1 pcie interrupt me ssage to pci interrupt mapping in reverse bridge mode pcie interrupt messages (from sources of interrupt) pci interrupts (to host controller) inta message inta intb message intb intc message intc intd message intd table 10-2 pci interrupt to pcie interrupt message mapping in forward bridge mode pci interrupts (from sources of interrupts) pcie interrupt message packets (to host controller) inta inta message intb intb message intc intc message intd intd message 11 eeprom (i2c) interface and system management bus
pi7c9x110 pcie-to-pci reversible bridge page 133 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 11.1 eeprom (i2c) interface pi7c9x110 supports eeprom interface through i2c bus. in eeprom interface, pin a2 is the eeprom clock (scl) and pin a1 is the eeprom data (sdl). when tm2 is strapped to low, tm1 selects eeprom interface or system management bus. to select eeprom (i2c) inte rface, tm1 needs to be set to low. when eeprom interface is selected, scl is an output. scl is the i2c bus clock to the i2c device. in addition, sdl is a bi- directional signal for se nding and receiving data. 11.2 system management bus pi7c9x110 supports sm bus protocol if tm1=1 when tm2 is strapped to low. in addition, smbclk (pin a2) and smbdat (pin a1) are utilized as the clock and data pins respectively for the sm bus. when sm bus interface is selected, smbclk pin is an inpu t for the clock of sm bus and smbdat pin is an open drain buffer that requires external pull-up resistor for proper operation. 12 hot plug operation pi7c9x110 is not equipped with standard hot-plug controller (shpc) integrated. however, pi7c9x110 supports hot-plug signaling messages and registers to simplify the implementation of hot-plug system. using pi7c9x110 on motherboard: ? pi7c9x110 supports hot-plug on pci bus if forward bridging is selected (revrsb=0). ? pi7c9x110 supports hot-plug function on pci express bus when reverse bridge mode is selected (revrsb=1). using pi7c9x110 on add-in card: ? pi7c9x110 supports hot-plug on pci express bus in forward bridge mode. hot-plug messages will be generated by pi7c9x110 based on the add-in card conditions. ? pi7c9x110 supports hot-plug function on pci bus when reverse bridge mode is selected. pi7c9x110 will tri-state the pci bus when reset is asserted. al so, pi7c9x110 will de-assert inta_l if reset is asserted. the state machine of pi7c9x110 pci bus inte rface will remain idle if the reset is asserted. after reset is de-asserted, pi7c9x110 will remain in idle state until an address phase containing a valid address for pi7c9x110 or its downstream devices. ? pi7c9x110 expects the refclk signal will be provided to its upstream pci express port prior to the de- assertion of reset. the downstream pci port of pi7c9x110 supports a range of frequency up to 66mhz. ? pi7c9x110 also supports subsystem vendor and subsystem id. pi7c9x 110 will ignore target response while the bus is idle. prsnt1# and prsnt2# are not implemented on both pi7c9x110. the use of these two signals is mandatory on an add-in card in order to support hot-plug. 13 reset scheme
pi7c9x110 pcie-to-pci reversible bridge page 134 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 pi7c9x110 requires the fundamental reset (perst_l) input for internal logic when it is set as forward bridge mode. pi7c9x110 requires the pci reset (reset_l) in put when it is set as reverse bridge mode. also, pi7c9x110 has a power-on-reset (por) circuit to detect vddcaux power supply for auxiliary logic control. ? cold reset: a cold reset is a fundamental or power-on reset that occu rs right after the power is applied to pi7c9x110 (during initial power up). see section 7.1.1 of pci express to pci bridge specification, revision 1.0 for details. ? warm reset: a warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to pi7c9x110. ? hot reset: a hot reset is a reset that used an in-band mechanism for propagating reset across a pcie link to pi7c9x110. pi7c9x110 will enter to traini ng control reset when it receives two consecu tive ts1 or ts2 order-s ets with reset bit set. ? dl_down reset: if the pcie link goes down, the transaction and data link layer will enter dl_down status. pi7c9x110 discards all transactions and returns all logic and registers to initial state except the sticky registers. upon receiving reset (cold, warm, ho t, or dl_down) on pcie interface , pi7c9x110 will generate pci reset (reset_l) to the downstream devices on the pci bus in forward bridge mode. the pci reset de-assertion follows the de-assertion of the reset received fr om pcie interface. the reset bit of bridge control register may be set depending on the application. pi7c 9x110 will tolerant to receive and pr ocess skip order-sets at an average interval between 1180 to 1538 symbol times. pi7c9x110 does not keep pci reset active when vd33 power is off even though vaux (3.3v) is supported. it is recommende d to add a weak pull-down resistor on its application board to ensure pci reset is low when vd33 power is off (see section 7.3.2 of pci bus power management specification revision 1.1). in reverse bridge mode, pi7c9x110 generates fundamental reset (perst_l) and then 1024 ts1 order-sets with reset bit set when pci reset (reset_l) is asserted to pi7c9x110. pi7c9x110 has scheduling skip order-set for insertion at an interval between 1180 and 1538 symbol times. pi7c9x110 transmits one electrical idle order-set and enters to electrical idle. 14 ieee 1149.1 compat ible jtag controller an ieee 1149.1 compatible test access port (tap) contro ller and associated tap pins are provided to support boundary scan in pi7c9x110 for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst_l. all digital input, output , input/output pins are tested except tap pins. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass and boundary scan registers. the tap controller is a synchronous 16-state machine driven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at po wer-up. the jtag signal lin es are not active when the pci resource is opera ting pci bus cycles. 14.1 instruction register
pi7c9x110 pcie-to-pci reversible bridge page 135 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 pi7c9x110 implements a 5-bit instruction register to control the operation of the jtag logic. the defined instruction codes are shown in table 14 -1. those bit combinations that are not listed are equivalent to the bypass (11111) instruction: table 14-1 instruction register codes instruction operation code (binary) register selected operation extest 00000 boundary scan drives / receives off-chip test data sample 00001 boundary scan samples inputs / pre-loads outputs highz 00101 bypass tri-states output and i/o pins except tdo pin clamp 00100 bypass drives pins from boundary-scan register and selects bypass register for shifts idcode 01100 device id accesses the device id register, to read manufacturer id, part number, and version number bypass 11111 bypass selected bypass register int_scan 00010 internal scan scan test mem_bist 01010 memory bist memory bist test 14.2 bypass register the required bypass register (one-bit shift register) provid es the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the pi7c9x110. 14.3 device id register this register identifies pericom as the manufacturer of the device and details the part number and revision number for the device. table 14-2 jtag device id register bit type value description 31:28 ro 01h version number 27:12 ro e110h last 4 digits (hex) of the die part number 11:1 ro 23fh pericom identifier assigned by jedec 0 ro 1b fixed bit equal to 1?b1 14.4 boundary scan register the boundary scan register has a set of serial shift-register cells. a chain of boundary scan cells is formed by connected the internal signal of the pi7c9x110 package pins. the vdd, vss, and jtag pins are not in the boundary scan chain. the input to the shift register is tdi and the output from the shift register is tdo. there are 4 different types of boundary scan cells, based on the function of each signal pin. the boundary scan register cells are dedi cated logic and do not have any system function. data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample and extest instructions. parallel lo ading takes place on the rising edge of tck. 14.5 jtag boundary sc an register order table 14-3 jtag boundary scar register definition
pi7c9x110 pcie-to-pci reversible bridge page 136 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 boundary scan register number pin name ball location type tri-state control cell 0 ad [0] k14 bidir 1 1 - - control - 2 ad [1] j11 bidir 3 3 - - control - 4 ad [2] j13 bidir 5 5 - - control - 6 ad [3] j14 bidir 7 7 - - control - 8 ad [4] h12 bidir 9 9 - - control - 10 ad [5] h13 bidir 11 11 - - control - 12 ad [6] g11 bidir 13 13 - - control - 14 ad [7] g12 bidir 15 15 - - control - 16 cbe [0] g14 bidir 17 17 - - control - 18 ad [8] f11 bidir 19 19 - - control - 20 ad [9] f13 bidir 21 21 - - control - 22 ad [10] f14 bidir 23 23 - - control - 24 ad [11] e13 bidir 25 25 - - control - 26 ad [12] d11 bidir 27 27 - - control - 28 ad [13] d12 bidir 29 29 - - control - 30 ad [14] d14 bidir 31 31 - - control - 32 ad [15] c12 bidir 33 33 - - control - 34 cbe [1] c14 bidir 35 35 - - control - 36 par b13 bidir 37 37 - - control - 38 serr_l b14 bidir 39 39 - - control - 40 perr_l a14 bidir 41 41 - - control - 42 lock_l a13 bidir 43 43 - - control - 44 stop_l a12 bidir 45 45 - - control - 46 devsel_l b11 bidir 47 47 - - control - 48 trdy_l a11 bidir 47 49 irdy_l d10 bidir 50 50 - - control - 51 frame_l b10 bidir 52 52 - - control - 53 cbe [2] a10 bidir 54 54 - - control - 55 ad [16] c9 bidir 56 56 - - control - 57 ad [17] b9 bidir 58 58 - - control - 59 ad [18] d8 bidir 60
pi7c9x110 pcie-to-pci reversible bridge page 137 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 boundary scan register number pin name ball location type tri-state control cell 60 - - control - 61 ad [19] c8 bidir 62 62 - - control - 63 ad [20] a8 bidir 64 64 - - control - 65 ad [21] d7 bidir 66 66 - - control - 67 ad [22] b7 bidir 68 68 - - control - 69 ad [23] a7 bidir 70 70 - - control - 71 cbe [3] c6 bidir 72 72 - - control - 73 ad [24] b6 bidir 74 74 - - control - 75 ad [25] d5 bidir 76 76 - - control - 77 ad [26] c5 bidir 78 78 - - control - 79 ad [27] a5 bidir 80 80 - - control - 81 ad [28] d4 bidir 82 82 - - control - 83 ad [29] b4 bidir 84 84 - - control - 85 ad [30] a4 bidir 86 86 - - control - 87 ad [31] b3 bidir 88 88 - - control - 89 pme_l a3 bidir 90 90 - - control - 91 smbclk a2 bidir 92 92 - - control - 93 smbdat a1 bidir 94 94 - - control - 95 clkrun_l d3 bidir 96 96 - - control - 97 fbclkin c2 input - 98 reserved 0 b1 input - 99 reserved 1 d2 output3 100 100 - - control - 101 perst_l l3 bidir 102 102 - - control - 103 req_l [0] m1 input - 104 req_l [1] m2 input - 105 req_l [2] m3 input - 106 req_l [3] n1 input - 107 req_l [4] n2 input - 108 req_l [5] n3 input - 109 req_l [6] p1 input - 110 req_l [7] p2 input - 111 inta_l p3 bidir 112 112 - - control - 113 gnt_l [0] m4 output3 114 114 - - control - 115 gnt_l [1] n4 output3 122 116 gnt_l [2] l5 output3 122 117 gnt_l [3] m5 output3 122 118 gnt_l [4] n5 output3 122 119 gnt_l [5] p5 output3 122
pi7c9x110 pcie-to-pci reversible bridge page 138 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 boundary scan register number pin name ball location type tri-state control cell 120 gnt_l [6] p6 output3 122 121 gnt_l [7] n6 output3 122 122 - - control - 123 intb_l m6 bidir 124 124 - - control - 125 clkin p7 input - 126 reset_l n7 bidir 126 127 - - control - 128 cfn_l m7 input - 129 gpio [3] l7 bidir 129 130 - - control - 131 gpio [2] p8 bidir 131 132 - - control - 133 gpio [1] m8 bidir 133 134 - - control - 135 gpio [0] l8 bidir 135 136 - - control - 137 clkout [0] p9 output3 145 138 clkout [1] n9 output3 145 139 clkout [2] l9 output3 145 140 clkout [3] p10 output3 145 141 clkout [4] m10 output3 145 142 clkout [5] l10 output3 145 143 clkout [6] n11 output3 145 144 clkout [7] p12 output3 145 145 clkout [8] n12 output3 145 146 - - control - 147 intc_l p13 bidir 148 148 - - control - 149 revrsb m12 input - 150 intd_l n13 bidir 151 151 - - control - 152 msk_in p14 input - 153 idsel n14 input - 15 power management pi7c9x110 supports d0, d3-hot, d3-cold power states. d1 and d2 states are not supported. the pci express physical link layer of the pi7c9x110 device supports th e pci express link power management with l0, l0s, l1, l2/l3 ready and l3 power states. for the pci port of pi7c9x110, it supports the standard pci power management states with b0, b1, b2 and b3. during d3-hot state, the main power supplies of vddp, vddc, and vd33 can be turned off to save power while keeping the vddaux, vd dcaux, and vaux with the auxiliary power supplies to maintain all necessary information to be restored to the full power d0 state. pi7c9x110 has been designed to have sticky registers that are powered by auxiliary power supplies. pme_l pin allows pc i devices to request power management state changes. along with the operating system and application software, pci devices can achieve optimum power saving by using pme_l in forward bridge mode. pi7c9x110 converts pme_l signal information to power management messages to the upstream switches or root complex. in reverse bridge mode, pi7c9x110 converts the power management event messages from pcie devices to the pme_l signal and continues to request power management state change to the host bridge. pi7c9x110 also supports aspm (active state power management) to facilitate the link power saving. pi7c9x110 supports beacon generation but does not support wake# signal.
pi7c9x110 pcie-to-pci reversible bridge page 139 of 144 pericom semiconductor ? confidential april 2010, revision 3.0
pi7c9x110 pcie-to-pci reversible bridge page 140 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 16 electrical and timing specifications 16.1 absolute maximum ratings table 16-1 absolute maximum ratings (above which the useful life may be impair ed. for user guidelines, not tested.) storage temperature -65 o c to 150 o c ambient temperature with power applied -40 o c to 85 o c pci express supply voltage to ground potential (vdda, vddp, vddc, vddaux, and vddcaux) -0.3v to 3.0v pci supply voltage to ground potential (vd33 and vaux) -0.3v to 3.6v dc input voltage for pci express signals -0.3v to 3.0v dc input voltage for pci signals -0.5v to 5.75v note: stresses greater than those listed under m aximum ratings may cause permanent dama ge to the device. this is a stress rating only and functional operation of the device at these or any conditions above t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi tions for extended periods of time may affect reliability. 16.2 dc specifications table 16-2 dc electrical characteristics power pins min. typ. max. vdda 1.6v 1.8v 2.0v vddp 1.6v 1.8v 2.0v vddc 1.6v 1.8v 2.0v vddaux 1.6v 1.8v 2.0v vddcaux 1.6v 1.8v 2.0v vtt vddc vddc 2.0v vd33 3.0v 3.3v 3.6v vaux 3.0v 3.3v 3.6v vdda: analog power supply for pci express interface vddp: digital power supply for pci express interface vddaux: digital auxiliary power supply for pci express interface vtt: termination power suppl y for pci express interface vddc: digital power power supply for the core vddcaux: digital auxiliary power supply for the core vd33: digital power supply for pci interface vaux: digital auxiliary powe r supply for pci interface in order to support auxiliary power management fully, it is recommended to have vddp and vddaux separated. by the same token, vd33/vddc and vaux/vddcaux need to be separate d for auxiliary power management support. however, if auxiliary power management is not required, vd33 and vddc can be connected to vaux and vddcaux respectively. the typical power consumption of pi7c9x110 is about 1.0 watt.
pi7c9x110 pcie-to-pci reversible bridge page 141 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 pi7c9x110 is capable of sustaining 2000v human body model for the esd protection without any damages. 16.3 ac specifications table 16-3 pci bus timing parameters 66 mhz 33 mhz symbol parameter min max min max units tsu input setup time to clk ? bused signals 1,2,3 3 - 7 - tsu (ptp) input setup time to clk ? point-to-point 1,2,3 5 - 10, 12 4 - th input signal hold time from clk 1,2 0 - 0 - tval clk to signal valid delay ? bused signals 1,2,3 2 6 2 11 tval (ptp) clk to signal valid delay ? point-to-point 1,2,3 2 6 2 12 ton float to active delay 1,2 2 - 2 - toff active to float delay 1,2 - 14 - 28 ns 1. see figure 16 ?1 pci signal timing measurement conditions. 2. all pci interface signals are synchronized to fbclkin. 3. point-to-point signals are req_l [7:0], gnt_l [7:0], loo, and enum_l. bused signals are ad, cbe, par, perr_l, serr_l, frame_l, irdy_l , trdy_l, lock_l, stop_l and idsel. 4. req_l signals have a setup of 10ns and gnt_l signals have a setup of 12ns. figure 16-1 pci signal timing conditions
pi7c9x110 pcie-to-pci reversible bridge page 142 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 17 package information figure 17-1 top view drawing figure 17-2 bottom view drawing
pi7c9x110 pcie-to-pci reversible bridge page 143 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 the package of pi7c9x110 is a 12mm x 12mm lfbga (160 pin) package. the ball pitch is 0.8mm and the ball size is 0.5mm. the following are the pa ckage information and mechanical dimension: figure 17-3 package outline drawing 18 ordering information part number pin ? package pb-free & green temperature range PI7C9X110BNBe 160 ? lfbga yes -40 to +85c PI7C9X110BNB 160 ? lfbga no -40 to +85c
pi7c9x110 pcie-to-pci reversible bridge page 144 of 144 pericom semiconductor ? confidential april 2010, revision 3.0 notes:

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